WCRT analysis for a uniprocessor with a unified prioritized cache

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2005, Pages 175-182

  Tan, Yudong ^a   Mooney III, Vincent J ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Cache Design; Real time System; Timing Analysis

Indexed keywords

MULTITASKING; REAL TIME SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); TIMING CIRCUITS;

CACHE DESIGN; TIMING ANALYSIS; WORST CASE RESPONSE TIME (WCRT);

PROGRAM PROCESSORS;

EID: 31844452947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065910.1065935     Document Type: Conference Paper

References (24)

1. J. Busquets-Mataix, J. Serrano, R. Ors, P. Gil, and A. Wellings. Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In Real-Time Technology and Applications Symposium, pages 204-212, June 1996.
2. S. Dropso. Comparing caching techniques for multitasking real-time systems. Technical report, University of Massachusetts, Amherst, UM-CS-1997-065, November 1997.
3. D. Kirk. Smart (strategic memory allocation for real-time) cache design. In Proceedings of the Real-Time Systems Symposium, pages 229-237, December 1989.
4. C. Lee, J. Hahn, Y. Seo, S. Min, R. Ha, S. Hong, C. Park, M. Lee, and C. Kim. Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In Proceedings of IEEE Real-Time Systems Symposium, pages 187-198, December 1997.
5. C. Lee, J. Hahn, Y. Seo, S. Min, R. Ha, S. Hong, C. Park, M. Lee, and C. Kim. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Transactions on Computers, 47(6):700-713, 1998.
6. Y. Li, S. Malik, and A. Wolfe. Performance estimation of embedded software with instruction cache modeling. ACM Transaction on Design Automation of Embedded Systems, 4(3):257-279, July 1999.
7. N. Maki, K. Hoson, and A. Ishida. A data-replace-controlled cache memory system and its performance evaluations. In Proceedings of the IEEE Region 10 Conference, pages 471-474, April 1999.
8. Mentor Graphics, XRAY® Debugger, http://www.mentor.com/xray/.
9. MediaBench, http://cares.icsl.ucla.edu/MediaBench/.
10. Mentor Graphics, Hardware/Software Co-Verification: Seamless. Available HTTP: http://www.mentor.com/seamless/.
11. F. Muller. Compiler support for software-based cache partitioning. In Proceedings of ACM SIGPLAN Workshop on Languages, Compliers and Tools for Real-Time Systems, pages 125-133, June 1995.
12. H. Negi, T. Mitra, and A. Roychoudhury. Accurate estimation of cache-related preemption delay. In Proceedings of ACM Joint Symposia CODES+ISSS, 2003.
13. G. Suh, S. Devadas, and L. Rudolph. Cache models with applications to cache partitioning. In Proceedings of the 15th international conference on Supercomputing, pages 1-12, June 2001.
14. G. Suh, L. Rudolph, and S. Devadas. Dynamic cache partitioning for simultaneous multithreading systems. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, pages 116-127, September 2001.
15. Synopsys, http://www.synopsys.com/products/simulation/simulation.html.
16. Y. Tan and V. Mooney. A prioritized cache for multi-tasking real-time systems. In Proceedings of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'03), pages 168-175, April 2003.
17. Y. Tan and V. Mooney. Timing analysis for preemptive multi-tasking real-time systems. In Proceedings of Design, Automation and Test in Europe (DATE'04), pages 1034-1039, February 2004.
18. Y. Tan and V. Mooney. Integrate inter- and intra- cache eviction anlaysis for preemptive multi-tasking real-time systems. In Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES'04), pages 200-206, September 2004.
19. Y. Tan. Cache Design and Timing Analysis for Preemptive Multitasking Real-Time Uniprocessor Systems. PhD Thesis, Georgia Institute of Technology, April 2005. Available HTTP: http://etd.gatech.edu.
20. K. Tindeil, A. Burns, and A. Wellings. An extendible approach for analyzing fixed priority hard real-time tasks. Real-Time Systems, 6(2):133-151, March 1994.
21. H. Tomiyama and N. Dutt. Program path analysis to bound cache-related preemption delay in preemptive real-time systems. In Proceedings of the Eighth International Workshop on Hardware/software Codesign, pages 67-71, May 2000.
22. X. Vera, B. Lisper, and J. Xue. Data cache locking for higher program predictability. In Proceedings of International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'03), pages 272-282, June 2003.
23. F. Wolf. Behavioral Intervals in Embedded Software. Kluwer Academic Publishers, 2002.
24. A. Wolfe. Software-based cache partitioning for real-time applications. In Proceedings of the 3rd Workshop on Responsive Computer Systems, September 1993.