Analyzing LTL model checking techniques for plan synthesis and controller synthesis (work in progress)

Electronic Notes in Theoretical Computer Science

Volumn 149, Issue 2, 2006, Pages 91-104

  Kerjean, Sylvain ^a   Kabanza, Froduald ^a   St Denis, Richard ^a   Thiébaux, Sylvie ^b  

^a UNIVERSITÉ DE SHERBROOKE   (Canada)

^b AUSTRALIAN NATIONAL UNIVERSITY   (Australia)

Author keywords

Formula progression; LTL2B chi translators; Model checking; Synthesis; Verification

Indexed keywords

BENCHMARKING; MATHEMATICAL MODELS; PROGRAM TRANSLATORS;

FORMULA PROGRESSION; MODEL CHECKING; SYNTHESIS; VERIFICATION;

CONTROL EQUIPMENT;

EID: 31644433450     PISSN: 15710661     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.entcs.2005.07.028     Document Type: Conference Paper

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