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Volumn 1, Issue , 2003, Pages 469-474

Hardware and software-in-the-loop techniques using the opnet modeling tool for JTRS developmental testing

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE IN THE LOOP (HITL); NETWORK CENTRIC SYSTEMS; SOFTWARE IN THE LOOP (SITL);

EID: 3142693518     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (5)
  • 2
    • 3142711069 scopus 로고    scopus 로고
    • Methodology for incorporating commercial off the shelf (COTS) network hardware into OPNET modeler for hardware-in-the-loop modeling & simulation
    • Washington DC, August
    • Martinez, R., W. Wu, "Methodology for Incorporating Commercial off the Shelf (COTS) Network Hardware into OPNET Modeler for Hardware-in-the-Loop Modeling & Simulation," OPNETWorks 2001 Symposium, Washington DC, August 2001.
    • (2001) OPNETWorks 2001 Symposium
    • Martinez, R.1    Wu, W.2
  • 3
    • 3142670032 scopus 로고    scopus 로고
    • OPNET Technologies Inc., Bethesda, MD
    • OPNET Modeler Documentation, OPNET Technologies Inc., Bethesda, MD, 2001.
    • (2001) OPNET Modeler Documentation
  • 4
    • 3142781621 scopus 로고    scopus 로고
    • U.S. Army Information Systems Engineering Command, Technology Integration Center, December
    • CUITN Core Switching Architecture Requirements Analysis, U.S. Army Information Systems Engineering Command, Technology Integration Center, December 2000.
    • (2000) CUITN Core Switching Architecture Requirements Analysis


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.