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Volumn 1, Issue , 2003, Pages 469-474
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Hardware and software-in-the-loop techniques using the opnet modeling tool for JTRS developmental testing
a
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Author keywords
[No Author keywords available]
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Indexed keywords
HARDWARE IN THE LOOP (HITL);
NETWORK CENTRIC SYSTEMS;
SOFTWARE IN THE LOOP (SITL);
COMPUTER HARDWARE;
COMPUTER SIMULATION;
COMPUTER SYSTEM FIREWALLS;
GATEWAYS (COMPUTER NETWORKS);
NETWORK PROTOCOLS;
REAL TIME SYSTEMS;
ROUTERS;
SOFTWARE ENGINEERING;
TELECOMMUNICATION TRAFFIC;
LARGE SCALE SYSTEMS;
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EID: 3142693518
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (8)
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References (5)
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