Low-power design techniques for scaled technologies

Integration, the VLSI Journal

Volumn 39, Issue 2, 2006, Pages 64-89

  Paul, Bipul C ^a,b,c,d   Agarwal, Amit ^a   Roy, Kaushik ^a,d  

^a PURDUE UNIVERSITY   (United States)

^b TOSHIBA CORPORATION   (Japan)

^c STANFORD UNIVERSITY   (United States)

^d IEEE   (United States)

Author keywords

Low leakage memory design; Low power design; Nanometer scale circuit design

Indexed keywords

LOW LEAKAGE MEMORY DESIGN; LOW POWER DESIGN; NANOMETER SCALE CIRCUIT DESIGN; POWER DENSITY;

DATA STORAGE EQUIPMENT; GROWTH (MATERIALS); INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON; VLSI CIRCUITS;

TRANSISTORS;

EID: 31344470671     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2005.12.001     Document Type: Article

References (75)

1. S. Borkar Design challenges of technology scaling IEEE Micro 19 4 1999 23
2. J. Brews, in: S.M. Sze (Ed.), High Speed Semiconductor Devices, Wiley, New York, 1990.
3. K. Roy, and S.C. Prasad Low-Power CMOS VLSI Circuit Design 2000 Wiley Interscience Publications New York
4. Y. Taur, and T.H. Ning Fundamentals of Modern VLSI Devices 1998 Cambridge University Press New York
5. R. Dennard, et al., Design of ion-implanted MOSFET's with very small physical dimensions, IEEE J. Solid State Circuits (1974) 256.
6. S. Mukhopadhyay, K. Roy, Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits, in: Symposium of VLSI Circuits, 2003.
7. K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits, Proc. IEEE (2003).
8. 2 breakdown model for very low voltage lifetime extrapolation IEEE Trans. Electron Devices 41 1994 761
9. C. Choi, K. Nam, Z. Yu, and R.W. Dutton Impact of gate direct tunneling current on circuit performance: a simulation study IEEE Trans. Electron Devices 48 2001 2823
10. K. Cao, et al., BSIM4 gate leakage model including source drain partition, in: IEDM Technical Digest, 2000, p. 815.
11. S. Mukhopadhyay, A. Raychowdhury, K. Roy, Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current model, in: Design Automation Conference (DAC), 2003, pp. 169-174.
12. T. Glokler, S. Bitterlich, H. Meyr, Increasing the power efficiency of application specific instruction set processors using datapath optimization, in: IEEE Workshop on Signal Processing Systems, 2000, pp. 563-570.
13. L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, Reducing power consumption of dedicated processors through instruction set encoding, in: Proceedings of the Eighth Great Lakes Symposium on VLSI, 1998, pp. 8-12.
14. K. Masselos, S. Theoharis, P. Merakos, T. Stouraitis, and C.E. Goutis Memory accesses reordering for interconnect power reduction in sum-of-products computations IEEE Trans. Signal Process. 50 2002 2889 2899
15. R. Saied, C. Chakrabarti, Scheduling for minimizing the number of memory accesses in low power applications, in: Workshop on VLSI Signal Processing, 1996, pp. 169-178.
16. J. Park, W. Jeong, H. Choo, H. Mahmoodi, Y. Wang, K. Roy, High performance and low power FIR filter design based on sharing multiplication, in: International Symposium on Low Power Electronics and Design (ISLPED'02), 2002, pp. 295-300.
17. D. Kang, H. Choo, K. Roy, Floorplan-aware low-complexity digital filter synthesis for low-power & high-speed, in: International Conference on Computer Design, 2004, pp. 354-357.
18. J.P. Fishburn, A.E. Dunlop, TILOS: a posynomial programming approach to transistor sizing, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1985) 326-328.
19. S. Sapatnekar, V.B. Rao, P.M. Vaidya, S.M. Kang, An exact solution of the transistor sizing problem for CMOS circuits using convex optimization, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1993) 1612-1634.
20. C.P. Chen, C.C.N. Chu, and D.F. Wong Fast and exact simulations gate and wire sizing by Lagrangian relaxation IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 1999 1014 1025
21. M.T. Bohr, Interconnect scaling-the real limiter to high performance ULSI, in: International Electron Device Meeting (IEDM) Technical Digest, 1995, pp. 241-244.
22. J.D. Meindl, Beyond Moore's law: the interconnect era, Comput. Sci. Eng. (2003) 20-24.
23. M.L. Mui, K. Banerjee, and A. Mehrotra A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth and power dissipation IEEE Trans. Electron Devices 51 2004 195 203
24. S. Katkoori, S. Alupoaei, RT-level interconnect optimization in DSM regime, in: IEEE Computer Society Workshop on VLSI, 2000, pp. 143-148.
25. Y. Cao, C. Hu, X. Huang, A.B. Kahng, S. Muddu, D. Stroobandt, D. Sylvester, Effects of global interconnect optimizations on performance estimation of deep submicron design, in: International Conference on Computer Aided Design, 2000, pp. 56-61.
26. A. Naeemi, R. Venkatesan, J.D. Meindl, System-on-a-chip global interconnect optimization, in: International SOC Conference, 2002, pp. 399-403.
27. D. Garrett, M. Stan, A. Dean, Challenges in clock gating for a low power ASIC methodology, in: International Symposium on Low Power Electronics and Design, 1999, pp. 176-181.
28. J. Oh, and M. Pedram Gated clock routing for low-power microprocessor design IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 2001 715 722
29. N. Raghavan, V. Akella, S. Bakshi, Automatic insertion of gated clocks at register transfer level, in: International Conference on VLSI Design, 1999, pp. 48-54.
30. L. Benini, and G.D. Micheli Automatic synthesis of low power gated clock finite state machines IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 1996 630 643
31. T. Fuse, A. Kameyama, M. Ohta, K. Ohuchi, A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology, in: Digest of Technical Papers of Symposium on VLSI Circuits, 2001, pp. 219-220.
32. L.R. Carley, A. Aggarwal, A completely on-chip voltage regulation technique for low power digital circuits, in: Proceedings of International Symposium on Low Power Electronics and Design, 1999, pp. 109-111.
33. Y. Kanno, H. Mizuno, K. Tanaka, T. Watanabe, Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs, in: Digest of Technical Papers of Symposium on VLSI Circuits, 2000, pp. 202-203.
34. V. Sundararajan, K.K. Parhi, Synthesis of low power CMOS VLSI circuits using dual supply voltages, in: Design Automation Conference, 1999, pp. 72-75.
35. K. Usami, M. Horowitz, Cluster voltage scaling techniques for low power design, in: International Symposium on Low Power Design, 1995, pp. 3-8.
36. C. Yeh, M. Chang, S. Chang, W. Jone, Gate level design exploiting dual supply voltages for power driven applications, in: Design Automation Conference, 1999, pp. 68-71.
37. M.C. Johnson, K. Roy, Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints, in: Proceedings of the International Conference on Computer Design (ICCD), 1996, pp. 72-77.
38. J. Chang, and M. Pedram Energy minimization using multiple supply voltages IEEE Trans. VLSI Syst. 5 1997 1 8
39. C. Chen, A. Srivastava, and M. Sarrafzadeh On gate level power optimization using dual supply voltages IEEE Trans. VLSI Syst. 9 2001 616 629
40. T. Kuroda, and M. Hamada Low power CMOS digital design with dual embedded adaptive power supplies IEEE J. Solid State Circuits 35 2000 652 655
41. T. Burd, T. Pering, A. Stratakos, and R. Brodersen A dynamic voltage scaled microprocessor system IEEE J. Solid State Circuits 35 11 2000 1571 1580
42. S. Lee, T. Sakurai, Run-time voltage hopping for low-power real-time systems, in: Proceedings of IEEE/ACM Design Automation Conference, 2000, pp. 806-809.
43. L. Hai, C. Chen, T.N. Vijaykumar, K. Roy, VSV: L2 miss driven variable supply voltage scaling for low power, in: International Symposium on Microarchitecture (MICRO), 2003, pp. 19-28.
44. L. Wei, Z. Chen, M. Johnson, K. Roy, Y. Ye, V. De, Design and optimization of dual threshold circuits for low voltage low power applications, IEEE Trans. VLSI Syst. 16 (1999).
45. T. Karnik, et al., Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, in: ACM/IEEE Design Automation Conference, 2002, p. 486.
46. J.T. Kao, and A.P. Chandrakasan Dual-threshold voltage techniques for low-power digital circuits IEEE J. Solid State Circuits 35 2000 1009
47. N. Sirisantana, L. Wei, K. Roy, High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness, in: Proceedings of the 2000 International Conference on Computer Design, 2000, p. 227.
48. K.A. Bowman, et al., Impact of die-to-die and within die parameter fluctions on the maximum clock frequency distribution for gigascale integration, IEEE J. Solid State Circuits (2002).
49. Y. Ye, S. Borkar, V. De, A new technique for standby leakage reduction in high performance circuits, in: IEEE Symposium on VLSI Circuits, 1998, p. 40.
50. Z. Chen, L. Wei, M. Johnson, K. Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, in: IEEE International Conference on Computer Aided Design, 1998.
51. Z. Chen, L. Wei, A. Keshavarzi, K. Roy, IDDQ testing for deep submicron ICs: challenges and solutions, IEEE Des. Test Comput. 24 (2002).
52. S. Mukhopadhyay, C. Neau, T. Cakici, A. Agarwal, C.H. Kim, K. Roy, Gate leakage reduction for scaled devices using transistor stacking, in: IEEE Transactions on Very Large Scale Integration Systems, 2003.
53. M.C. Johnson, D. Somasekhar, K. Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS, in: Proceedings of ACM/IEEE Design Automation Conference, 1999. p. 442.
54. S. Mutoh 1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS IEEE J. Solid State Circuits 30 1995 847
55. J. Kao, A. Chandrakasan, D. Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, in: Proceedings of ACM/IEEE Design Automation Conference, 1997, p. 495.
56. H. Kawaguchi, K. Nose, T. Sakurai, A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current, in: Digest of Technical Papers of IEEE International Solid-State Circuits Conference, 1998, p. 192.
57. S. Heo, K. Asanovic, Leakage-biased domino circuits for dynamic fine-grain leakage reduction, in: Symposium on VLSI Circuits, 2002, p. 316.
58. T. Kuroda, et al., A 0.9 V 150 MHz 10 mW 4 mm 2-D discrete cosine transform core processor with variable-threshold-voltage scheme, in: Digest of Technical Papers of IEEE International Solid-State Circuits Conference, 1996, p. 166.
59. A. Keshavarzi, C.F. Hawkins, K. Roy, V. De, Effectiveness of reverse body bias for low power CMOS circuits, in: Proceedings of Eighth NASA Symposium on VLSI Design, 1999, p. 231.
60. S. Narendra, et al., IEEE J. Solid State Circuits (2003).
61. H. Mizuno, et al., An 18-?A standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode, IEEE J. Solid State Circuits 34 (1999).
62. C.H. Kim, K. Roy, Dynamic Vth scaling scheme for active leakage power reduction, in: Design, Automation and Test in Europe, 2002, p. 163.
63. K. Nose, et al., Vth-hopping scheme for 82% power saving in low-voltage processors, in: Proceedings of IEEE Custom Integrated Circuits Conference, 2001, p. 93.
64. A. Agarwal, H. Li, K. Roy, A single-Vt low-leakage gated-ground cache for deep submicron, IEEE J. Solid State Circuits (2003).
65. H. Yamauchi, et al., A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme, in: Symposium on VLSI Circuits, 1996, p. 126.
66. A.J. Bhavnagarwala, A. Kapoor, J.D. Meindl, Dynamic threshold CMOS SRAMs for fast, portable applications, in: ASIC/SOC Conference, 2000, p. 359.
67. K. Osada, et al., 16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors, in: International Solid-State Circuits Conference, 2003, p. 302.
68. A. Agarwal, K. Roy, Noise tolerant cache design to reduce gate and subthreshold leakage in nanometer regime, in: International Symposium of Low Power Electronics and Design (ISLPED2003), 2003, pp. 18-21.
69. H. Kawaguchi, Y. Itaka, T. Sakurai, Dynamic leakage cut-off scheme for low-voltage SRAM's, in: Symposium on VLSI Circuits, 1998, p. 140.
70. C.H. Kim, K. Roy, Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors, in: International Symposium of Low Power Electronics and Design, 2002, p. 251.
71. C.H. Kim, et al., ISLPED 2003.
72. K. Flautner, et al., Drowsy caches: simple techniques for reducing leakage power, in: International Symposium on Computer Architecture, 2002, p. 148.
73. S. Heo, et al., Dynamic fine-grain leakage reduction using leakage-biased bitlines, in: International Symposium on Computer Architecture, 2002, p. 137.
74. K. Itoh, A.R. Fridi, A. Bellaouar, M.I. Elmasry, A deep sub-V, single power-supply SRAM cell with multi-Vt, boosted storage node and dynamic load, in: Symposium on VLSI Circuits Digest of Technical Papers, 1996, p. 132.
75. L. Hai, S. Bhunia, Y. Chen, K. Roy, and T.N. Vijaykumar DCG: deterministic clock gating for low-power microprocessor design IEEE Trans. VLSI Syst. 12 2004 245 254