Design and implementation of a shared buffer architecture for a gigabit ethernet packet switch

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2005, Pages 283-286

  O'Kane, Stephen ^a   Sezer, Sakir ^a   Toal, Ciaran ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER CIRCUITS; COMPUTER NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS; PACKET NETWORKS; STANDARDS;

BUFFER ARCHITECTURE; BUFFER BANDWIDTH; BUFFERING; IMPLEMENTATION;

COMPUTER ARCHITECTURE;

EID: 30844451804     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. "10 Gigabit Ethernet: An enabler for high-performance storage networking", Cisco White Paper
2. "Gigabit Ethernet jumbo frames", Phil Dykstra, http://sd.wareonearth.com/~phil/jumbo.html
3. http://www.bell-labs.eom/org/11347A/project/projects.html
4. Bin Zhou, M. Atiquzzaman, "Analysis of window by-pass mechanism in split shared buffer ATM switch", ATNAC'95, Sydney, Australia, 11-13 December 1995
5. N. Endo et al., "Shared buffer memory switch for an ATM exchange," IEEE Trans. Commun., vol. 41, no. 1, Jan. 1993, pp. 23745.
6. H. Kuwahara, "A shared buffer memory switch for an ATM exchange", IEEE GLOBECOM, 1989.
7. M. Devault, J. Cochennec, "The prelude ATD experiment: Assessments and Future Prospects", IEEE JSAC, 1988
8. M. Henrion, "Switching network architecture for ATM based broad communications", ISS 90.
9. W.E. Denzel, "A flexible shared-buffer switch for ATM at Gb/s rates", Journal on Computer networks and ISND systems, 1995.