Process and temperature performance of a CMOS beta-multiplier voltage reference

Midwest Symposium on Circuits and Systems

Volumn , Issue , 1998, Pages 33-36

  Liu, Song ^a   Baker, R Jacob ^a  

^a University of Idaho Boise Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TEMPERATURE; VOLTAGE MEASUREMENT;

BANDGAP VOLTAGE REFERENCE; DIRECT REPLACEMENTS; PROCESS VARIATION; SUBSTRATE CURRENT; SUPPLY SENSITIVITY; TEMPERATURE COEFFICIENT; TEMPERATURE PERFORMANCE; VOLTAGE REFERENCE;

CMOS INTEGRATED CIRCUITS;

EID: 30844443847     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.1998.759429     Document Type: Conference Paper

References (3)

1. R. Jacob Baker, Harry W. Li and Davis E. Boyce: "CMOS Circuit Design, Layout, and Simulation ", IEEE Press 1999.
2. Hoi-Jun Yoo, Seung-Jun Lee, Jeong-Tae Kwon, Wi-Sik Min and Kye-Hwan Oh, "A Precision CMOS Voltage Reference with Enhanced Stability for the Application to Advanced VLSI's", ISCAS 1993.
3. E. Vittoz and J. Fellrah, "CMOS Analog Integrated Circuits Bused on Weak Inversion Operation", IEEE Journal of Solid State Circuits, Vol. SC-12, No.3, June 1977, pp.224-231.