SCOPUS 정보 검색 플랫폼

Volumn 22, Issue , 2003, Pages 59-70

Effects of surface preparation on high-k gate stack device performance

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITION (ALD); GATE LEAKAGE; GATE TRANSISTORS;

ANNEALING; DEPOSITION; DIELECTRIC DEVICES; LEAKAGE CURRENTS; METALLORGANIC CHEMICAL VAPOR DEPOSITION; OZONE; THIN FILMS; THRESHOLD VOLTAGE;

TRANSISTORS;

EID: 3042854499 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (7)

References (10)

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- (2000) Appl. Phys. Letts. , vol.76 , pp. 436
- Copel, M.¹ Gribelyuk, M.² Gusev, E.³

3
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- B. H. Lee, R. Choi, L. Kang, S. Goplan, R. Nieh, K. Onishi, Y. Jeon, W. -J. Qi, C. Kang and J. C. Lee, IEDM Tech. Digest, 39-41 (2000)
- (2000) IEDM Tech. Digest , pp. 39-41
- Lee, B.H.¹ Choi, R.² Kang, L.³ Goplan, S.⁴ Nieh, R.⁵ Onishi, K.⁶ Jeon, Y.⁷ Qi, W.-J.⁸ Kang, C.⁹ Lee, J.C.¹⁰

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- L. Kang, K. Onishi, Y. Jeon, B. Lee, C. Kang, W. Qi, R. Nieh, S. Gopalan, R. Choi and J. C. Lee, IEDM Tech Digest, 35-37 (2000)
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- (2001) Symp. VLSI Technology Digest , pp. 133-134
- Lee, S.J.¹ Luan, H.F.² Bai, W.P.³ Jeon, T.S.⁴ Bai, W.P.⁵ Senzaki, Y.⁶ Roberts, D.⁷ Kwong, D.L.⁸

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.