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Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2001-January, Issue , 2001, Pages 123-128

Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking

(1) Johannsen, P a

a SIEMENS AG (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; FORMAL LOGIC; HARDWARE; MODEL CHECKING; RECONFIGURABLE HARDWARE;

DESIGN ABSTRACTIONS; EQUIVALENT SYSTEM; ORIGINAL SYSTEMS; PROPERTY CHECKING; REDUCTION TECHNIQUES; SATISFIABILITY PROBLEMS; SYSTEM OF EQUATIONS; VERIFICATION TECHNIQUES;

BOOLEAN ALGEBRA;

EID: 3042647730 PISSN: 15526674 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/HLDVT.2001.972818 Document Type: Conference Paper

Times cited : (8)

References (10)

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- Barrett, C.W.¹ Dill, D.L.² Levitt, J.R.³

2
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- Symbolic Model Checking Using SAT Procedures instead of BDDs
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3
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- Binary Decision Diagrams and Beyond: Enabling Techniques for Formal Verification
- R. E. Bryant. "Binary Decision Diagrams and Beyond: Enabling Techniques for Formal Verification". In Proc. ICCAD, pages 236-243, 1995.
- (1995) Proc. ICCAD , pp. 236-243
- Bryant, R.E.¹

4
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- An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
- D. Cyrluk, M. O. Möller, and H. Ruess. "An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors". In Proc. CAV, pages 60-71, 1997.
- (1997) Proc. CAV , pp. 60-71
- Cyrluk, D.¹ Möller, M.O.² Ruess, H.³

5
- 0033714214
- Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
- C. Y. Huang and K. T. Cheng. "Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques". In Proc. DAC, pages 118-123, 2000.
- (2000) Proc. DAC , pp. 118-123
- Huang, C.Y.¹ Cheng, K.T.²

6
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- BOOSTER : Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction
- P. Johannsen. "BOOSTER : Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction". In Proc. CAV'01, pages 373-377, 2001.
- (2001) Proc. CAV'01 , pp. 373-377
- Johannsen, P.¹

7
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- PhD thesis, Christian-Albrechts-University of Kiel
- P. Johannsen. "Scaling Down Design Sizes in Hardware Verification". PhD thesis, Christian-Albrechts-University of Kiel, to appear in 2001.
- (2001) Scaling Down Design Sizes in Hardware Verification
- Johannsen, P.¹

8
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- PhD thesis, University of Michigan
- J. P. M. Silva. "Search Algorithms for Satisfiability Problems in Combinational Switching Circuits". PhD thesis, University of Michigan, 1995.
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9
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- Boolean satisfiability in electronic design automation
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10
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- Zeng, Z.¹ Kalla, P.² Ciesielski, M.³

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