Dynamic memory disambiguation in the presence of out-of-order store issuing

Journal of Instruction-Level Parallelism

Volumn 4, Issue , 2002, Pages

  Önder, Soner ^a   Gupta, Rajiv ^b  

^a Michigan Technological University   (United States)

^b University of Arizona   (United States)

Author keywords

Instruction window; Memory disambiguation; Speculative execution; Store set; Wide issue superscalar

Indexed keywords

INSTRUCTION WINDOWS; MEMORY DISAMBIGUATION; SPECULATIVE EXECUTION; STORE-SETS; WIDE-ISSUE SUPERSCALARS;

ALGORITHMS; CODES (SYMBOLS); DATA STORAGE EQUIPMENT; INTEGER PROGRAMMING; ITERATIVE METHODS; PROGRAM PROCESSORS; SET THEORY;

PARALLEL PROCESSING SYSTEMS;

EID: 3042641453     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (11)

1. Brad Calder, Glenn Reinman, and Dean M. Tullsen. Selective value prediction. In Proceedings of the 26th International Conference on Computer Architecture, pages 64-74, May 1999.
2. George Z. Chrysos and Joel S. Emer. Memory dependence prediction using store sets. In Proceedings of the 25th International Conference on Computer Architecture, pages 142-153, June 1998.
3. J. Hesson, J. LeBlanc, and S. Ciavaglia. Apparatus to dynamically control the Out-Of-Order execution of Load-Store instructions. US. Patent 5,615,350, Filed Dec. 1995, Issued Mar. 1997.
4. Stephan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, and Adi Yoaz. Predictive techniques for aggressive load speculation. In The 31st Annual IEEE-ACM International Symposium on Microarchitecture, pages 216-225, December 1998.
5. Mikko H. Lipasti and John Paul Shen. Exceeding the dataflow limit via value prediction. In Proceedings of the 29th Annual A CM/IEEE International Symposium on Microarchitecture, pages 226-237, 1996.
6. Mikko H. Lipasti, Christopher B. Wilkerson, and John Paul Shen. Value locality and load value prediction. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), pages 138-147, October 1996.
7. Andreas I. Moshovos. Memory Dependence Prediction. PhD thesis, University of Wisconsin - Madison, 1998.
8. Andreas I. Moshovos, Scott E. Breach, T. N. Vijaykumar, and Gurindar S. Sohi. Dynamic speculation and synchronization of data dependences. In Proceedings of the 24th International Conference on Computer Architecture, pages 181-193, June 1997.
9. Soner Önder and Rajiv Gupta. Automatic generation of microarchitecture simulators. In IEEE International Conference on Computer Languages, pages 80-89, Chicago, May 1998.
10. Glenn Reinman and Brad Calder. Predictive techniques for aggressive load speculation. In The 31st Annual IEEE-ACM International Symposium on Microarchitecture, pages 127-137, December 1998.
11. S. Steely, D. Sager, and D. Fite. Memory reference tagging. US. Patent 5.619,662, Filed Aug. 1994, Issued Apr. 1997.