Wire retiming for system-on-chip by fixpoint computation

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1092-1097

  Lin, Chuan ^a   Zhou, Hai ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

POLYNOMIAL TIME APPROXIMATION SCHEME; SYSTEM-ON-CHIPS (SOC); WIRE RETIMING; FIXPOINT COMPUTATIONS; INTERNAL STRUCTURE; ITERATIVE ALGORITHM; LONG INTERCONNECT; MULTIPLE ORDERS; OPERATION TIME; SYSTEM ON CHIPS; WIRE SEGMENTS;

ALGORITHMS; COMPUTATIONAL METHODS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC DESIGN; POLYNOMIAL APPROXIMATION; PROBLEM SOLVING; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; EXHIBITIONS; MICROPROCESSOR CHIPS;

CHIP SCALE PACKAGES; WIRE;

EID: 3042615332     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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