Transmission line pulse measurements: A tool for developing ESD robust integrated circuits

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 1-6

  Ashton, R A ^a  

^a White Mountain Labs   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; PRODUCT DESIGN; RELIABILITY;

ELECTROSTATIC DISCHARGES; HUMAN BODY MODEL (HBM); TRANSMISSION LINE PULSE (TLP) MEASUREMENTS;

ELECTRIC LINES;

EID: 3042615142     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits. John Wiley & Sons, 2002.
2. JEDEC Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), EIA/JESD22-A114-B, June 2000. (Available from www.jedec.org)
3. ESDA Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM) Component Level, ESD STM5.1-2001, Rome, NY, 13440, 2001.
4. J. Barth, J. Richner, L. Henry, M. Kelly, "Real HBM & MM - The dV/dt Threat" EOS/ESD Symposium Proceedings 2003, pp. 179-187 Las Vegas, NV September 2003.
5. JEDEC "Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)", EIA/JESD22-A115-A, June 2000. (Available from www.jedec.org)
6. ANSI/ESDA Electrostatic Discharge Sensitivity Testing - Machine Model (MM) Component Level, ANSI/ESD STM5.2-1999, Rome, NY, 13440, 1999.
7. JEDEC Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components EIA/JESD22-C101-A, June 2000. (Available from www.jedec.org)
8. ANSI/ESDA Charged Device Model (CDM)-Component Level, ANSI/BSD STM5.3.1-1999, Rome, NY, 13440, 1999.
9. T. Maloney and N. Khurana, "Transmission Line Pulseing techniques for Circuit Modeling of ESD Phenomena" EOS/ESD Symposium Proceedings 1995, pp. 49-54, Minneapolis, MN, September 1985.
10. ESDA "Electrostatic Discharge Sensitivity Testing Transmission Line Pulse (TLP), ESD DSP5.5.1-2003, Rome, NY, 13440, June 2003
11. J. Barth, K. Verhaege, L. Henry, and J. Richner, "TLP Calibration, Correlation, Standards, and New Techniques" EOS/ESD Symposium 2000, pp. 85-96, Anaheim, CA, September 2000.
12. E. Worley, R Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, Sub-Micron Chip "ESD Protection Schemes which Avoid Avalanching Junctions" EOS/ESD Symposium Proceedings 1995, pp. 13-20, Phoenix, AZ, September 1995.
13. H. Gieser and M. Haunschild, "Very-Fast transmission Line Pulsing of Integrated Structures and the Charged Device Model" EOS/ESD Symposium 1996, pp. 85-94, Orlando, FL September 1996.