Design and measurements of test element group wafer thinned to 10 μm for 3D system in package

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 161-164

  Ikeda, Akihiro ^a   Kuwata, Tomonori ^a   Kajiwara, Satoru ^a   Fujimura, Tsuyoshi ^a   Kuriyaki, Hisao ^a   Hattori, Reiji ^a   Ogi, Hiroshi ^b   Hamaguchi, Kiyoshi ^b   Kuroki, Yukinori ^a  

^a KYUSHU UNIVERSITY   (Japan)

^b Hara Seiki Industry Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CRYSTAL DEFECTS; DIGITAL CIRCUITS; DIODES; ELECTRIC CONDUCTIVITY; HEAT RADIATION; MOSFET DEVICES; PASSIVATION; THRESHOLD VOLTAGE;

ELECTRO-CHEMICAL PLATING; INTERCONNECTION BUMPS; TEST ELEMENT GROUPS (TEG);

SILICON WAFERS;

EID: 3042611449     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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