PMOS thin gate oxide recovery upon negative bias temperature stress

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2004, Pages 683-684

  Akbar, Mohammad S ^a   Agostinelli, Marty ^b   Rangan, Sanjay ^b   Lau, Shing ^b   Castillo, Cesar ^b   Pae, Sangwoo ^b   Kashyap, Sridhar ^b  

^a The University of Texas at Austin   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE OXIDES; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); STATIC STRESSING;

DEGRADATION; ELECTRIC FIELDS; LOGIC GATES; PASSIVATION; STRESSES; THRESHOLD VOLTAGE;

MOS DEVICES;

EID: 3042520504     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. V. Reddy et al., p. 248, 2002 IRPS
2. T. Yamamoto et al., p.921, IEEE Trans. Elect. Dev., May 1999
3. S. Rangan and N. Mielke, accepted for 2003 IEDM
4. K. Kuhn et al., p. 73, 2002 IEDM