A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn , Issue , 2004, Pages 312-317

  Menichelli, F ^a   Olivieri, M ^a   Benini, L ^b   Donno, M ^c   Bisdounis, L ^d  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c Bulldast Srl   (Italy)

^d Intracom Holdings SA   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION SET SIMULATORS (ISS); SOFTWARE MAPPING; SOFTWARE PROFILING; SYSTEM-ON-CHIP (SOC);

C (PROGRAMMING LANGUAGE); COMPUTER ARCHITECTURE; COMPUTER PERIPHERAL EQUIPMENT; COMPUTER SIMULATION; CONSTRAINT THEORY; INTERFACES (COMPUTER); ITERATIVE METHODS; LOCAL AREA NETWORKS; NETWORK PROTOCOLS; OPTIMIZATION; PROJECT MANAGEMENT;

MICROPROCESSOR CHIPS;

EID: 3042518926     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269256     Document Type: Conference Paper

References (11)

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