Saving power by mapping finite-state machines into embedded memory blocks in FPGAs

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 916-921

  Tiwari, Anurag ^a   Tomko, Karen A ^a  

^a University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CHIPS (ASIC); FINITE STATE MECHANICS (FSM); POWER CONSUMPTION; SYNCHRONOUS EMBEDDED MEMORY BLOCKS (SEMB); AREA MINIMIZATION; CLOCK FREQUENCY; CONTROL UNIT; EMBEDDED MEMORY BLOCKS; FINITE-STATE; MEMORY BLOCKS; ON CHIP MEMORY; ROUTING OVERHEADS;

ENERGY UTILIZATION; FLIP FLOP CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; RANDOM ACCESS STORAGE; ROM; ROUTERS; SYNCHRONIZATION; TABLE LOOKUP; CLOCKS; EXHIBITIONS;

MICROPROCESSOR CHIPS; LOGIC CIRCUITS;

EID: 3042517219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269007     Document Type: Conference Paper

References (14)

1. Xilinx Incorporate, San Jose California, Virtex-II data sheet, version 2.3, March 2003
2. Altera Corporation, Stratix Programmable Logic Device Family Data Sheet, version 2.0, April 2002
3. Actel Corporation, 42MX FPGA Data Sheet, ver 5.0, Feb' 01
4. L.Shang et al, "Dynamic Power Consumption in Virtex™-II FPGA family", Proc. FPGA '03, ACM Feb 2002
5. G.Sutter et al, "FSM Decomposition for Low Power in FPGA", Proc. FPL'02
6. J.Cong et al, "Technology Mapping for FPGAs with Embedded Memory Blocks", Proc. FPGA'98, ACM,
7. S.Wilton, "Heterogeneous Technology Mapping for FPGAs with Dual-Port Embedded Memory Array", Proc. FPGA'00, ACM, pp. 67-74
8. L.Benini et al, "Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines", IEEE Trans., CAD of IC, vol. 15 No.6 June 1996
9. Bob Lisanke. Logic synthesis and optimization benchmarks. Technical report, MCNC, Research Triangle Park, North Carolina, December 1988.
10. Programmable Electronic Performance Group, "PREP Benchmark Suite #4, Version 1.3," Los Altos, CA, 1994.
11. E. Sentovich, et al, SIS: A System for Seq. Circuit Synthesis. Tech. Report Mem. No. UCB/ ERL M92/41, Univ. of California, Berkeley, 1992.
12. Z. Kohavi, Switching and Finite Automata Theory. McGraw-Hill New York, 1978
13. Mitra, S. et al., "An Output Encoding Problem and a Solution Technique", IEEE Trans.CAD, vol. 18, no. 6, June'99
14. Binger, D. et al., "Encoding Multiple Outputs for Improved Column Compaction", Proc. ICCAD-91, 1991, pp. 230-233