Analysis and design of a robust average current mode control loop for parallel buck DC-DC converters to reduce line and load disturbance

IEE Proceedings: Electric Power Applications

Volumn 151, Issue 4, 2004, Pages 414-424

  Garcera G ^a   Figueres, E ^a   Pascual, M ^a   Benavent, J M ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL SYSTEM ANALYSIS; CONTROL SYSTEM SYNTHESIS; ELECTRIC CURRENT CONTROL; ELECTRIC POTENTIAL; PERFORMANCE; ROBUSTNESS (CONTROL SYSTEMS); STABILITY;

AVERAGE CURRENT MODE CONTROL LOOP; PARALLEL BUCK DC DC CONVERTERS;

POWER CONVERTERS;

EID: 3042517212     PISSN: 13502352     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-epa:20040319     Document Type: Article

References (12)

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