SCOPUS 정보 검색 플랫폼

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1334-1339

Systemverilog for VHDL users

(1) Fitzpatrick, Tom a

a SYNOPSYS INC (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTI-DIMENSIONAL ARRAYS; SIMULATION SCHEDULING; SYNTAXES; VERILOG; DATA TYPE; EVOLUTIONARY PATH; LANGUAGE FEATURES; MULTIDIMENSIONAL ARRAYS; SOC DESIGNS; SYSTEMVERILOG; VERIFICATION METHODOLOGY;

COMPUTER SIMULATION; FUNCTIONS; INTERFACES (COMPUTER); OBJECT ORIENTED PROGRAMMING; SCHEDULING; SEMANTICS; DESIGN; EXHIBITIONS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 3042511711 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/DATE.2004.1269080 Document Type: Conference Paper

Times cited : (6)

References (4)

1
- 3042617258
- SystemVerilog: Is this the merging of verilog and VHDL?
- September
- Clifford E. Cummings, "SystemVerilog: Is This the Merging of Verilog and VHDL?" SNUG (Synopsys Users Group Boston) Proceedings, September 2003
- (2003) SNUG (Synopsys Users Group Boston) Proceedings
- Cummings, C.E.¹

2
- 2942618905
- EEE Computer Society, IEEE, New York, NY, IEEE Std 1364-1995
- IEEE Standard Hardware Description Language Based on the Verflog Hardware Description Language, IEEE Computer Society, IEEE, New York, NY, IEEE Std 1364-1995
- IEEE Standard Hardware Description Language Based on the Verflog Hardware Description Language

3
- 2942618905
- IEEE Computer Society, IEEE, New York, NY, IEEE Std 1364-2001
- IEEE Standard Verflog Hardware Description Language, IEEE Computer Society, IEEE, New York, NY, IEEE Std 1364-2001
- IEEE Standard Verflog Hardware Description Language

4
- 2942661301
- Accellera
- SystemVerilog 3.1 Accellera's Extensions to Verilog, Accellera, 2003 freely downloadable from: www.systemverilog.org
- (2003) SystemVerilog 3.1 Accellera's Extensions to Verilog

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.