-
2
-
-
85006812375
-
"Accurately Modeling Speculative Instruction Fetching in Trace-Driven Simulation"
-
R. Bhargava, L.K. John, and F. Matus, "Accurately Modeling Speculative Instruction Fetching in Trace-Driven Simulation," Proc. Int'l Performance, Computing. and Comm. Conf., pp. 65-71, 1999.
-
(1999)
Proc. Int'l. Performance, Computing. and Comm. Conf.
, pp. 65-71
-
-
Bhargava, R.1
John, L.K.2
Matus, F.3
-
3
-
-
21644436760
-
"Aggressive Execution Engines for Surpassing Single Basic Block Execution"
-
PhD thesis, Univ. of Michigan
-
M.G. Butler, "Aggressive Execution Engines for Surpassing Single Basic Block Execution," PhD thesis, Univ. of Michigan, 1993.
-
(1993)
-
-
Butler, M.G.1
-
4
-
-
0030651783
-
"Predicting Indirect Jumps Using a Target Cache"
-
P.-Y. Chang, E. Hao, and Y.N. Patt, "Predicting Indirect Jumps Using a Target Cache," Proc. 24th Ann. Int'l Symp. Computer Architecture, pp. 274-283, 1997.
-
(1997)
Proc. 24th Ann. Int'l Symp. Computer Architecture
, pp. 274-283
-
-
Chang, P.-Y.1
Hao, E.2
Patt, Y.N.3
-
5
-
-
4644226058
-
"Mcroarchitecture Optimizations for Exploiting Memory-Level Parallelism"
-
Y. Chou, B. Fahs, and S. Abraham, "Mcroarchitecture Optimizations for Exploiting Memory-Level Parallelism," Proc. 31st Ann. Int'l Symp. Computer Architecture, pp. 76-87, 2004.
-
(2004)
Proc. 31st Ann. Int'l Symp. Computer Architecture
, pp. 76-87
-
-
Chou, Y.1
Fahs, B.2
Abraham, S.3
-
6
-
-
84878623481
-
"Mispredicted Path Cache Effects"
-
J. Combs, C.B. Combs, and J.P. Shen, "Mispredicted Path Cache Effects," Proc. Fifth Int'l Euro-Par Conf. Parallel Processing, pp. 1322-1331, 1999.
-
(1999)
Proc. Fifth Int'l Euro-Par Conf. Parallel Processing
, pp. 1322-1331
-
-
Combs, J.1
Combs, C.B.2
Shen, J.P.3
-
7
-
-
0030662863
-
"Improving Data Cache Performance by Pre-Executing Instructions under a Cache Miss"
-
J. Dundas and T. Mudge, "Improving Data Cache Performance by Pre-Executing Instructions under a Cache Miss," Proc. 1997 Int'l Conf. Supercomputing, pp. 68-75, 1997.
-
(1997)
Proc. 1997 Int'l Conf. Supercomputing
, pp. 68-75
-
-
Dundas, J.1
Mudge, T.2
-
8
-
-
8344236686
-
"Effective Stream-Based and Execution-Based Data Prefetching"
-
S. Iacobovici, L. Spracklen, S. Kadambi, Y. Chou, and S.G. Abraham, "Effective Stream-Based and Execution-Based Data Prefetching," Proc. 18th Int'l Conf. Supercomputing, pp. 1-11, 2004.
-
(2004)
Proc. 18th Int'l Conf. Supercomputing
, pp. 1-11
-
-
Iacobovici, S.1
Spracklen, L.2
Kadambi, S.3
Chou, Y.4
Abraham, S.G.5
-
9
-
-
0025429331
-
"Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers"
-
N.P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. 17th Ann. Int'l Symp. Computer Architecture, pp. 364-373, 1990.
-
(1990)
Proc. 17th Ann. Int'l Symp. Computer Architecture
, pp. 364-373
-
-
Jouppi, N.P.1
-
11
-
-
0029748076
-
"The Effects of Mispredicted-Path Execution on Branch Prediction Structures"
-
S. Jourdan, T.-H. Hsing, J. Stark, and Y.N. Patt, "The Effects of Mispredicted-Path Execution on Branch Prediction Structures," Proc. 1996 Int'l Conf. Parallel Architectures and Compilation Techniques, pp. 58-67, 1996.
-
(1996)
Proc. 1996 Int'l Conf. Parallel Architectures and Compilation Techniques
, pp. 58-67
-
-
Jourdan, S.1
Hsing, T.-H.2
Stark, J.3
Patt, Y.N.4
-
12
-
-
0029190803
-
"Instruction Cache Fetch Policies for Speculative Execution"
-
D. Lee, J.-L. Baer, B. Calder, and D. Grunwald, "Instruction Cache Fetch Policies for Speculative Execution," Proc. 22nd Ann. Int'l Symp. Computer Architecture, pp. 357-367, 1995.
-
(1995)
Proc. 22nd Ann. Int'l Symp. Computer Architecture
, pp. 357-367
-
-
Lee, D.1
Baer, J.-L.2
Calder, B.3
Grunwald, D.4
-
13
-
-
0031594012
-
"Pipeline Gating: Speculation Control for Energy Reduction"
-
S. Manne, A. Klauser, and D. Grunwald, "Pipeline Gating: Speculation Control for Energy Reduction," Proc. 25th Ann. Int'l Symp. Computer Architecture, pp. 132-141, 1998.
-
(1998)
Proc. 25th Ann. Int'l Symp. Computer Architecture
, pp. 132-141
-
-
Manne, S.1
Klauser, A.2
Grunwald, D.3
-
14
-
-
0003506711
-
"Combining Branch Predictors"
-
Technical Report TN-36, Digital Western Research Laboratory, June
-
S. McFarling, "Combining Branch Predictors," Technical Report TN-36, Digital Western Research Laboratory, June 1993.
-
(1993)
-
-
McFarling, S.1
-
16
-
-
16244421338
-
"Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance"
-
O. Mutlu, H. Kim, D.N. Armstrong, and Y.N. Patt, "Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance," Proc. 16th Symp. Computer Architecture and High Performance Computing, pp. 2-9, 2004.
-
(2004)
Proc. 16th Symp. Computer Architecture and High Performance Computing
, pp. 2-9
-
-
Mutlu, O.1
Kim, H.2
Armstrong, D.N.3
Patt, Y.N.4
-
17
-
-
77954452886
-
"Understanding the Effects of Wrong-Path Memory References on Processor Performance"
-
June
-
O. Mutlu, H. Kim, D.N. Armstrong, and Y.N. Patt, "Understanding the Effects of Wrong-Path Memory References on Processor Performance," Proc. Third Workshop Memory Performance Issues, pp. 56-64, June 2004.
-
(2004)
Proc. Third Workshop Memory Performance Issues
, pp. 56-64
-
-
Mutlu, O.1
Kim, H.2
Armstrong, D.N.3
Patt, Y.N.4
-
18
-
-
84955506994
-
"Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors"
-
O. Mutlu, J. Stark, C. Wilkerson, and Y.N. Patt, "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors," Proc. Ninth Int'l Symp. High Performance Computer Architecture, pp. 129-140, 2003.
-
(2003)
Proc. Ninth Int'l Symp. High Performance Computer Architecture
, pp. 129-140
-
-
Mutlu, O.1
Stark, J.2
Wilkerson, C.3
Patt, Y.N.4
-
21
-
-
0032785290
-
"A Study of Control Independence in Superscalar Processors"
-
E. Rotenberg, Q. Jacobson, and J.E. Smith, "A Study of Control Independence in Superscalar Processors," Proc. Fifth Int'l Symp. High Performance Computer Architecture, pp. 115-124, 1999.
-
(1999)
Proc. Fifth Int'l Symp. High Performance Computer Architecture
, pp. 115-124
-
-
Rotenberg, E.1
Jacobson, Q.2
Smith, J.E.3
-
22
-
-
84956866618
-
"Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions"
-
R. Sendag, D.J. Lilja, and S.R. Kunkel, "Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions," Proc. Eighth Int'l Euro-Par Conf. Parallel Processing, pp. 468-480, 2002.
-
(2002)
Proc. Eighth Int'l Euro-Par Conf. Parallel Processing
, pp. 468-480
-
-
Sendag, R.1
Lilja, D.J.2
Kunkel, S.R.3
-
23
-
-
0003535436
-
"POWER4 System Microarchitecture"
-
IBM Technical White Paper, Oct
-
J. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy, "POWER4 System Microarchitecture," IBM Technical White Paper, Oct. 2001.
-
(2001)
-
-
Tendler, J.1
Dodson, S.2
Fields, S.3
Le, H.4
Sinharoy, B.5
-
24
-
-
1342320051
-
"The Memory Gap and the Future of High Performance Memories"
-
Mar
-
M.V. Wilkes, "The Memory Gap and the Future of High Performance Memories," ACM Computer Architecture News, vol. 29, no. 1, pp. 2-7, Mar. 2001.
-
(2001)
ACM Computer Architecture News
, vol.29
, Issue.1
, pp. 2-7
-
-
Wilkes, M.V.1
|