Design and evaluation of hardware pseudo-random number generator MT19937

IEICE Transactions on Information and Systems

Volumn E88-D, Issue 12, 2005, Pages 2876-2879

  Konuma, Shiro ^a,b   Ichikawa, Shuichi ^a  

^a TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

^b Chuo System Corporation   (Japan)

Author keywords

Custom circuit; FPGA; Mersenne Twister; Random number; Simulation

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC PROGRAMMING; PROGRAM PROCESSORS;

CUSTOM CIRCUIT; MERSENNE TWISTER; RANDOM NUMBER;

RANDOM NUMBER GENERATION;

EID: 30344448872     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e88-d.12.2876     Document Type: Conference Paper

References (6)

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2. M. Matsumoto, "Mersenne Twister: A random number generator," http://www.math.sci.hiroshima-u.ac. jp/~m-mat/MT/mt.html
3. T. Kurokawa and S. Fujimoto, "Development of Mersenne Twister using CPLDs," IEICE Trans. Inf. & Syst. (Japanese Edition), vol.J84-D-I, no.5, pp.501-504, May 2001.
4. T. Kurokawa and H. Kajisaki, "FPGA based implementation of Mersenne Twister," Scientific and Engineering Reports of the National Defense Academy, vol.40, no.2, pp.15-21, March 2003.
5. Altera Corp., Stratix Device Handbook, July 2003. http://www.altera.com/
6. M. Matsumoto and T. Nishimura, "Dynamic creation of pseudorandom number generators," in Monte Carlo and Quasi-Monte Carlo Methods 1998, pp.56-69, Springer, 2000.