An alpha immune and ultra low neutron ser high density SRAM

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 671-672

  Roche, Philippe ^a   Jacquet, Francois ^a   Caillat, Christian ^a   Schoellkopf, Jean Pierre ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INFRARED RADIATION; IONIZING RADIATION; MICROPROCESSOR CHIPS; NEUTRON IRRADIATION; RADIATION HARDENING; SEMICONDUCTOR DEVICES;

CMOS TECHNOLOGY; HIGH DENSITY SRAM; MEMORY CELL; MEMORY NODES; NEUTRON SER; OPERATING VOLTAGE; SOFT ERROR; TERRESTRIAL RADIATION;

STATIC RANDOM ACCESS STORAGE;

EID: 29444433544     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315444     Document Type: Conference Paper

References (4)

1. P. Roche et al., "Comparisons of Soft Error Rate for SRAMs in Commercial SOI and Bulk below the 130 nm Technology Node", IEEE Trans. Nucl. Sci., vol. 40, Dec. 2003.
2. R. Baumann, "SER tutorial", Proceeding IEDM2001.
3. JEDEC standard n° JESD89, www.jedec.org.
4. J. Stinson et al., "A 1.5GHz Third Generation Itanium Processor", Proceeding 1SSCC 2003, February 2003.