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Volumn , Issue , 2004, Pages 253-258

A divide-and-conquer algorithm for 3D capacitance extraction

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOUNDARY ELEMENT METHOD; COMPUTATION THEORY; COMPUTER SIMULATION; ELECTRIC CONDUCTORS; MATRIX ALGEBRA; PROBLEM SOLVING;

EID: 2942666102     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.570695     Document Type: Conference Paper
Times cited : (4)

References (12)
  • 1
    • 0029734640 scopus 로고    scopus 로고
    • Modeling and extraction of interconnect capacitance for multilayer VLSI circuits
    • Jan.
    • N. D. Arora, et al., "Modeling and extraction of interconnect capacitance for multilayer VLSI circuits," IEEE Trans. CAD, Jan. 1996, 58-67.
    • (1996) IEEE Trans. CAD , pp. 58-67
    • Arora, N.D.1
  • 2
    • 0031380255 scopus 로고    scopus 로고
    • An error indicator and automatic adaptive meshing for electrostatic boundary element simulations
    • Dec.
    • M. Bachtold, et al., "An error indicator and automatic adaptive meshing for electrostatic boundary element simulations," IEEE Trans. CAD, Dec. 1997, 1439-1446.
    • (1997) IEEE Trans. CAD , pp. 1439-1446
    • Bachtold, M.1
  • 3
    • 0034157087 scopus 로고    scopus 로고
    • A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver
    • March
    • M. Bachtold, et al., "A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver, " IEEE Trans. CAD, March 2000, 325-338.
    • (2000) IEEE Trans. CAD , pp. 325-338
    • Bachtold, M.1
  • 4
    • 0033092804 scopus 로고    scopus 로고
    • Error bounds for capacitance extraction via window techniques
    • March
    • M. W. Beattie and L. T. Pileggi, "Error bounds for capacitance extraction via window techniques," IEEE Trans. CAD, March 1999, 311-321.
    • (1999) IEEE Trans. CAD , pp. 311-321
    • Beattie, M.W.1    Pileggi, L.T.2
  • 5
    • 0033346511 scopus 로고    scopus 로고
    • Electromagnetic parasitic extraction via a multipole method with hierarchical refinement
    • M. Beattie and L. Pileggi, "Electromagnetic parasitic extraction via a multipole method with hierarchical refinement," Proc. 1999 ICCAD, 437-444.
    • Proc. 1999 ICCAD , pp. 437-444
    • Beattie, M.1    Pileggi, L.2
  • 6
    • 0029239056 scopus 로고
    • A decomposition of multidimensional point sets with applications to k-nearest-neighbors and n-body potential fields
    • Jan.
    • P. B. Callahan and S. R. Kosaraju, "A decomposition of multidimensional point sets with applications to k-nearest-neighbors and n-body potential fields," J. ACM, Jan. 1995, 67-90.
    • (1995) J. ACM , pp. 67-90
    • Callahan, P.B.1    Kosaraju, S.R.2
  • 8
    • 0031335587 scopus 로고    scopus 로고
    • 3: A fast integral equation solver for efficient 3-dimensional extraction
    • 3: A fast integral equation solver for efficient 3-dimensional extraction," Proc. 1997 ICCAD, 448-455.
    • Proc. 1997 ICCAD , pp. 448-455
    • Kapur, S.1    Long, D.E.2
  • 9
    • 0033685330 scopus 로고    scopus 로고
    • Large-scale capacitance calculation
    • S. Kapur and D. E. Long, "Large-scale capacitance calculation, " Proc. 2000 DAC, 744-749.
    • Proc. 2000 DAC , pp. 744-749
    • Kapur, S.1    Long, D.E.2
  • 10
    • 0026255002 scopus 로고
    • FastCap: A multipole accelerated 3-D capacitance extraction program
    • Nov.
    • K. Nabors and J. White, "FastCap: A multipole accelerated 3-D capacitance extraction program," IEEE Trans. CAD, Nov. 1991, 1447-1459.
    • (1991) IEEE Trans. CAD , pp. 1447-1459
    • Nabors, K.1    White, J.2
  • 11
    • 0001573539 scopus 로고    scopus 로고
    • A pre-corrected FFT method for capacitance extraction of complicated 3-D structures
    • Oct.
    • J. R. Phillips and J. White, "A pre-corrected FFT method for capacitance extraction of complicated 3-D structures," IEEE Trans. CAD, Oct. 1997, 1059-1072.
    • (1997) IEEE Trans. CAD , pp. 1059-1072
    • Phillips, J.R.1    White, J.2
  • 12
    • 0036494536 scopus 로고    scopus 로고
    • A fast hierarchical algorithm for 3-D capacitance extraction
    • March
    • W. Shi, et al., "A fast hierarchical algorithm for 3-D capacitance extraction," IEEE Trans. CAD, March 2002, 330-336.
    • (2002) IEEE Trans. CAD , pp. 330-336
    • Shi, W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.