Hardware compilation of sequential ada

CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2001, Pages 99-107

  Ward, M ^a   Audsley, N C ^a  

^a UNIVERSITY OF YORK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERACTIVE COMPUTER SYSTEMS; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAM PROCESSORS;

CONCURRENCY MODELING; HARDWARE COMPILATION; MODERN PROCESSORS; REAL-TIME LANGUAGES; TIMING ANALYSIS; TIMING MODELING; TIMING SPECIFICATIONS; WORST-CASE EXECUTION TIME;

REAL TIME SYSTEMS;

EID: 2942569230     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/502217.502233     Document Type: Conference Paper

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