Fault simulation and response compaction in full scan circuits using HOPE

IEEE Transactions on Instrumentation and Measurement

Volumn 54, Issue 6, 2005, Pages 2310-2328

  Das, Sunil R ^a,b   Ramamoorthy, Chittoor V ^c   Assaf, Mansour H ^a   Petriu, Emil M ^a   Jone, Wen Ben ^d   Sahinoglu, Mehmet ^b  

^a UNIVERSITY OF OTTAWA   (Canada)

^b TROY UNIVERSITY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d 705 Engineering Research Center   (United States)

Author keywords

Built in self test (BIST); Circuit under test (CUT); Detectable error probability estimates; Fault simulation using HOPE; Hamming distance; Optimal sequence mergeability; Response compaction; Sequence weights; Single stuck line faults; Space compactor

Indexed keywords

BUILT-IN SELF TEST; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; ERRORS; ESTIMATION; PROBABILITY; SEQUENTIAL CIRCUITS;

CIRCUIT UNDER TEST (CUT); DETECTABLE ERROR PROBABILITY ESTIMATES; FAULT SIMULATION; HAMMING DISTANCE; OPTIMAL SEQUENCE MERGEABILITY; RESPONSE COMPACTION; SEQUENCE WEIGHTS; SINGLE STUCK-LINE FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 29244444535     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2005.858102     Document Type: Article

References (62)

1. A. Miczo. Digital Logic Testing and Simulation. New York: Harper and Row, 1986.
2. P.H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Technique. New York: Wiley, 1987.
3. R. Rajsuman, System-on-a-Chip: Design and Test. Boston, MA: Artech House, 2000.
4. S. Mourad and Y. Zorian, Principles of Testing Electronic Systems. New York: Wiley, 2000.
5. K. Chakrabarty, V. Iyengar, and A. Chandra, Test Resource Partitioning for System-on-a-Chip. Boston, MA: Kluwer, 2002.
6. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, K. Chakrabarty, Ed., Kluwer, Boston, MA, 2002.
7. P. K. Lala, Fault Tolerant and Fault Testable Hardware Design. London, U.K.: Prentice-Hall, 1985.
8. T. W. Williams and K. P. Parker, "Testing logic networks and design for testability," Computer, vol. 21, pp. 9-21, Oct. 1979.
9. S. M. Thatte and J. A. Abraham, "Test generation for microprocessors," IEEE Trans. Comput., vol. C-29, pp. 429-441, Jun. 1980.
10. J. R. Kuban and W. C. Bruce, "Self-testing the Motorola MC6804P2," IEEE Des. Test Comput., vol. 1, pp. 33-41, Oct. 1984.
11. E. J. McCluskey, "Built-in self-test techniques," IEEE Des. Test Comput., vol. 2, pp. 21-28, Apr. 1985.
12. R. G. Daniels and W. B. Bruce, "Built-in self-test trends in Motorola microprocessors," IEEE Des. Test Comput., vol. 2, pp. 64-71, Apr. 1985.
13. S. R. Das, "Built-in self-testing of VLSI circuits," IEEE Potentials, vol. 10, pp. 23-26, Oct. 1991.
14. V. D. Agrawal, C. R. Kime, and K. K. Saluja, "A tutorial on built-in self-test - Part II," IEEE Des. Test Comput., vol. 10, pp. 69-77, Jun. 1993.
15. Y. Zorian, "A distributed BIST control scheme for complex VLSI devices," in Proc. VLSI Test Symp., 1993, pp. 6-11.
16. H. J. Wunderlich and G. Kiefer, "Scan-based BIST with complete fault coverage and low hardware overhead," in Proc. Euro. Test Workshop, 1996, pp. 60-64.
17. Y. Zorian, "Test requirements for embedded core-based systems and IEEE P-1500," in Proc. Int. Test Conf., 1997, pp. 191-199.
18. P. Varma and S. Bhatia, "A structured test reuse methodology for corebased system chip," in Proc. Int. Test Conf., 1997, pp. 294-302.
19. J. Brauch and J. Fleischman, "Design of cache test hardware on the HP PA8500," IEEE Des. Test Comput., vol. 15, pp. 58-63, Jun. 1998.
20. R. Fetherston, "Testability features of the AMD-K6 microprocessor," IEEE Des. Test Comput., vol. 15, pp. 64-69, Jun. 1998.
21. A. Carbine, "Pentium Pro processor design for test and debug," IEEE Des. Test Comput., vol. 15, pp. 77-82, Jun. 1998.
22. K. Chakrabarty and S. R. Das, "Test-set embedding based on width compression for mixed-mode BIST," IEEE Trans. Instrum. Meas., vol. 49, pp. 671-678, Jun. 2000.
23. S. R. Das, "Self-testing of embedded cores-based systems with built-in hardware," in Proc. IEE, Cir. Dev. Syst., vol. 152, Oct. 2005, pp. 539-546.
24. J. P. Hayes, "Check sum methods for test data compression," J. Design Automat. Fault-Tolerant Comput., vol. 1, pp. 3-7, Jan. 1976.
25. J. P. Hayes, "Transition count testing of combinational logic circuits," IEEE Trans. Comput., vol. C-25, pp. 613-620, Jun. 1976.
26. R. A. Frohwerk, "Signature analysis-A new digital field service method," Hewlett-Packard J3., vol. 28, pp. 2-8, May 1977.
27. J. Savir, "Syndrome-testable design of combinational circuits," IEEE Trans. Comput., vol. C-29, pp. 442-451, Jun. 1980.
28. A. K. Susskind, "Testing by verifying Walsh coefficients," IEEE Trans. Comput., vol. C-32, pp. 198-201, Feb. 1983.
29. T-C. Hsiao and S. C. Seth, "An analysis of the use of Rademacher-Walsh spectrum in compact testing," IEEE Trans. Comput., vol. C-33, pp. 934-937, Oct. 1984.
30. T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, "Aliasing errors in signature analysis registers," IEEE Des. Test Comput., vol. 4, pp. 39-45, Apr. 1987.
31. S. B. Akers, "A parity bit signature for exhaustive testing," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. CAD-7, pp. 333-338, Mar. 1988.
32. W. -B. Jone and S. R. Das, "Multiple-output parity bit signature for exhaustive testing," J. Electron. Test. Theory Applicat., vol. 1, pp. 175-178, Jun. 1990.
33. D. K. Pradhan and S. K. Gupta, "A new framework for designing and analyzing BIST techniques and zero aliasing compression," IEEE Trans. Comput., vol. C-40, pp. 743-763, Jun. 1991.
34. S. R. Das, M. Sudarma, M. H. Assaf, E. M. Petriu, W. -B. Jone, K. Chakrabarty, and M. Sahinoglu, "Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets," IEEE Trans. Instrum. Meas., vol. 52, pp. 1363-1380, Oct. 2003.
35. N. R. Saxena and J. P. Robinson, "A unified view of test response compression methods," IEEE Trans. Comput., vol, C-36, pp. 94-99, Jan. 1987.
36. K. K. Saluja and M. Karpovsky, "Testing computer hardware through compression in space and time," in Proc. Int. Test Conf., 1983, pp. 83-88,
37. Y. Zorian and V. K. Agarwal, "A general scheme to optimize error masking in built-in self testing," in Proc. Int. Symp. Fault-Tolerant Computing, 1986, pp. 410-415.
38. Y. K. Li and J. P. Robinson, "Space compression method with output data modification," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. CAD-6, pp. 290-294, Mar. 1987.
39. S. M. Reddy, K. K. Saluja, and M. G. Karpovsky, "Data compression technique for test responses," IEEE Trans. Comput., vol. C-37, pp. 1151-1157, Sep. 1988.
40. M. Karpovsky and P. Nagvajara, "Optimal robust compression of test responses," IEEE Trans. Comput., vol. C-39, pp. 138-141, Jan. 1990.
41. W. -B. Jone and S. R. Das, "Space compression method for built-in selftesting of VLSI circuits," Int. J. Comput. Aided VLSI Design, vol. 3, pp. 309-322, Sep. 1991.
42. S. R. Das, H. T. Ho, W. -B. Jone, and A. R. Nayak, "An improved output compaction technique for built-in self-test in VLSI circuits," in Proc. Int. Conf. VLSI Design, 1994, pp. 403-407.
43. K. Chakrabarty and J. P. Hayes, "Efficient test response compression for multiple-output circuits," in Proc. Int. Test Conf., 1994, pp. 501-510.
44. S. R. Das, M. Assaf, and A. R. Nayak, "On the design of space compressor for VLSI circuits in BIST using nonexhaustive test sets," Trans. SDPS, vol. 2, pp. 1-12, Dec. 1998.
45. B. Pouya and N. A. Touba, "Synthesis of zero-aliasing elementary-tree space compactors," in Proc. VLSI Test Symp., 1998, pp. 70-77.
46. S. R. Das, T. F. Barakat, E. M. Petriu, M. H. Assaf, and K. Chakrabarty, "Space compression revisited," IEEE Trans. Instrum. Meas., vol. 49, pp. 690-705, Jun. 2000.
47. M. Seuring and K. Chakrabarty, "Space compaction of test responses for IP cores using orthogonal transmission functions," in Proc. VLSI Test Symp., 2000, pp. 1-7.
48. S. R. Das, M. H. Assaf, E. M. Petriu, W. -B. Jone, and K. Chakrabarty, "A novel approach to designing aliasing-free space compactors based on switching theory formulation," in Proc. IEEE Instrum. Meas. Tech. Conf., vol. 1, 2001, pp. 198-201.
49. S. R. Das, C. V. Ramamoorthy, M. H. Assaf, E. M. Petriu, and W. -B. Jone, "Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities," IEEE Trans. Instrum. Meas., vol. 50, pp. 1725-1747, Dec. 2001.
50. S. R. Das, J. Y. Liang, E. M. Petriu, W. -B. Jone, and K. Chakrabarty, "Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering," IEEE Trans. Instrum. Meas., vol. 51, pp. 150-172, Feb. 2002.
51. S. R. Das, M. H. Assaf, E. M. Petriu, and W. -B. Jone, "Fault simulation and response compaction in full scan circuits using HOPE," in IEEE Instrum. Meas. Tech. Conf., vol. 1, 2002, pp. 607-612.
52. S. Mitra and K. S. Kim, "X-compact: An efficient response compaction technique for test cost reduction," in Proc. Int. Test Conf., 2002, pp. 311-320.
53. M. B. Tahoori, S. Mitra, S. Toutounchi, and E. J. McCluskey, "Fault grading FPGA test configuration," in Proc. Int. Test Conf., 2002, pp. 608-617.
54. J. Rajski, J. Tyszer, C. Wang, and S. M. Reddy, "Convolutional compaction of test responses," in Proc. Int. Test Conf., 2003, pp. 745-754,
55. S. R. Das, M. H. Assaf, E. M. Petriu, and M. Sahinoglu, "Aliasing-free compaction in testing cores-based system-on-chip (SOC) using compatibility of response data outputs," Trans. SDPS, vol. 8, pp. 1-17, Mar. 2004.
56. K. Chakrabarty, "Test response compaction for built-in self testing," Ph.D. dissertation, Dept. of Computer Science and Engineering, Univ. of Michigan, Ann Arbor, MI, 1995.
57. M. H. Assaf, "Digital core output test data compression architecture based on switching theory concepts," Ph.D. dissertation, School of Information Technology and Engineering, Univ. of Ottawa, Ottawa, ON, Canada, 2003.
58. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. New York: W. H. Freeman, 1979.
59. H. K. Lee and D. S. Ha, "On the generation of test patterns for combinational circuits," Dept. of Electrical Engineering, Virginia Polytechnic Inst. and State Univ., Blacksburg, VA, Tech. Rep. 12-93, 1993.
60. H. K. Lee and D. S. Ha, "HOPE: An efficient parallel fault simulator for synchronous sequential circuits," in Proc. Des. Automation Conf., 1992, pp. 336-340.
61. H. K. Lee and D. S. Ha, "An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation," in Proc. Int. Test Conf., 1991, pp. 946-955.
62. I. Pomeranz, L. N. Reddy, and S. M. Reddy, "COMPACTEST: A method to generate compact test sets for combinational circuits," in Proc. Int. Test Conf., 1991, pp. 194-203.