An equivalence checking methodology for hardware oriented C-based specifications

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2002-January, Issue , 2002, Pages 139-144

  Saito, H ^a   Ogawa, T ^b   Sakunkonchak, T ^b   Fujita, M ^b   Nanya, T ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Debugging; Design engineering; Feedback; Hardware; High level synthesis; Productivity; Reduced instruction set computing; Resource management; Scheduling; Very large scale integration

Indexed keywords

COMPUTER DEBUGGING; COMPUTER HARDWARE; FEEDBACK; HARDWARE; HIGH LEVEL SYNTHESIS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; PRODUCTIVITY; REDUCED INSTRUCTION SET COMPUTING; SCHEDULING; SPECIFICATIONS; VLSI CIRCUITS;

BASED SPECIFICATION; DESIGN ENGINEERING; DESIGN FLOWS; EQUIVALENCE CHECKING; RESOURCE MANAGEMENT; SYMBOLIC SIMULATION; TEXTUAL DIFFERENCE; VLSI DESIGN;

DESIGN;

EID: 29144497389     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2002.1224443     Document Type: Conference Paper

References (8)

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