FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E88-A, Issue 12, 2005, Pages 3516-3521

  Hariyama, Masanori ^a   Kobayashi, Yasuhiro ^b   Sasaki, Haruka ^a   Kameyama, Michitaka ^a,c  

^a TOHOKU UNIVERSITY   (Japan)

^b OYAMA NATIONAL COLLEGE OF TECHNOLOGY   (Japan)

^c IEEE

Author keywords

Allocation; FPGA; Scheduling; Stereo vision

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; IMAGE PROCESSING; INTERCONNECTION NETWORKS; SCHEDULING; STEREO VISION;

ALLOCATION; OVERLAPPING REGIONS; STEREO MATCHING; WINDOW SIZE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 29144450031     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e88-a.12.3516     Document Type: Article

References (5)

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4. M. Hariyama, T. Takeuchi, and M. Kameyama, "VLSI processor for reliable stereo matching based on adaptive window-size selection," Proc. International Conference on Robotics and Automation, pp.1168-1173, 2001.
5. M. Hariyama and M. Kameyama, "VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture," Digest of Technical Paper 2004 Symposium on VLSI Circuits VLSI Symposium, pp.166-169, 2004.