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Volumn , Issue , 2005, Pages 157-165

Single Appearance Schedule with Dynamic Loop Count for Minimum Buffer from Synchronous Dataflow Graphs

Author keywords

Automatic Code Synthesis; Dynamic Loop Count; Memory Optimization; Single Appearance Schedule; Synchronous Dataflow

Indexed keywords

CODES (SYMBOLS); DATA PROCESSING; DATA STORAGE EQUIPMENT; GRAPH THEORY; SCHEDULING;

EID: 29144444668     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (18)
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    • Data memory minimization for synchronous data flow graphs emulated on dsp-fpga targets
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  • 6
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    • Apgan and rpmc: Complementary heuristics for translating dsp block diagrams into efficient software implementations
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    • S. S. Bhattachayya, P. K. Murthy, and E. A. Lee. Apgan and rpmc: Complementary heuristics for translating dsp block diagrams into efficient software implementations. In Journal of Design Automation for Embedded Systems, volume 2, pages 33-60, January 1997.
    • (1997) Journal of Design Automation for Embedded Systems , vol.2 , pp. 33-60
    • Bhattachayya, S.S.1    Murthy, P.K.2    Lee, E.A.3
  • 11
    • 0023138886 scopus 로고
    • Static scheduling of synchronous dataflow programs for digital signal processing
    • January
    • E. A. Lee and D. G. Messerschmitt. Static scheduling of synchronous dataflow programs for digital signal processing. In IEEE Transaction on Computer, volume C-36, pages 24-35, January 1987.
    • (1987) IEEE Transaction on Computer , vol.C-36 , pp. 24-35
    • Lee, E.A.1    Messerschmitt, D.G.2
  • 14
    • 0037870809 scopus 로고    scopus 로고
    • Memory-optimized software synthesis from dataflow program graphs with large size data samples
    • May
    • H. Oh and S. Ha. Memory-optimized software synthesis from dataflow program graphs with large size data samples. In EURASIP Journal on Applied Signal Processing, volume 2003, pages 514-529, May 2003.
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    • Oh, H.1    Ha, S.2
  • 16
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    • Scheduling for optimum data memory compaction in block diagram oriented software synthesis
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    • S. Ritz, M. Willems, and H. Meyr. Scheduling for optimum data memory compaction in block diagram oriented software synthesis. In Proceedings of the ICASSP 95, May 1995.
    • (1995) Proceedings of the ICASSP 95
    • Ritz, S.1    Willems, M.2    Meyr, H.3
  • 17
    • 0034289987 scopus 로고    scopus 로고
    • Memory efficient software synthesis using mixed coding style from dataflow graph
    • October
    • W. Sung and S. Ha, Memory efficient software synthesis using mixed coding style from dataflow graph. In IEEE Transaction on VLSI Systems, volume 8, pages 522-526, October 2000.
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    • Sung, W.1    Ha, S.2
  • 18
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    • Evolutionary algorithm based exploration of software schedules for digital signal processors
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    • E. Zitzler, J. Teich, and S. S. Bhattacharyya. Evolutionary algorithm based exploration of software schedules for digital signal processors. In Proceedings of the Genetic and Evolutionary Computation Conference, volume 2, pages 1762-1770, Orlando, Florida, USA, 13-17 1999. Morgan Kaufmann.
    • (1999) Proceedings of the Genetic and Evolutionary Computation Conference , vol.2 , pp. 1762-1770
    • Zitzler, E.1    Teich, J.2    Bhattacharyya, S.S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.