A 10 b 100 Ms/s pipelined subranging BiCMOS ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1993, Pages 66-67

  Sone, K ^a   Nakadai, N ^a   Nishida, Y ^a   Ishida, M ^a   Sekine, Y ^a   Yotsuyanagi, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; DIGITAL TO ANALOG CONVERSION; ERROR CORRECTION; OPERATIONAL AMPLIFIERS; PIPELINES; SIGNAL TO NOISE RATIO;

ACQUISITION TIME; ADC(ANALOG-TO-DIGITAL CONVERTER); CONVERSION RATES; CORRECTION FUNCTION; DISTORTION RATIO; INPUT FREQUENCY; POLYSILICON CAPACITORS; SAMPLE-AND HOLD AMPLIFIER;

ANALOG TO DIGITAL CONVERSION;

EID: 29044449986     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1993.280081     Document Type: Conference Paper

References (4)

1. Zojer, B., et al., "A 10b 75MHz SubrangingMI Converter", ISSCC DIGEST OF TECHNICAL. PAPERS, pp. 164-165, Feb. 1990.
2. Lane, C., "A 10-BIT60 MSPSFLASHADC", ProceedingsofBCTM, pp. 44-47, Sept. 1989.
3. Yotsuyanagi, M., et al., "A l2Bit 5usec CMOS Recursive ADC with 25mW Power Consumption", Proceedings of CICC, pp. 6.4.1-4, May 1989.
4. Sone, K., et al., "An 8-bit 20MHz Subranging ADC with Internal Clamp and S/H Circuits", ICCE Digest of Technical Papers, pp. 248-249, June 1990.