Determination of the acceleration factor between wafer level and package level electromigration test

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2005, Pages 658-659

  Federspiel, X ^a   Ney, D ^b   Girault, V ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28744444474     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Korhonen M.A., Borgesen P., J. Appl. Phys. Vol 73, 8, 1993.
2. Federspiel X., Girault V., Ney D., IRW, 2003.
3. Choi. Z.-S., Gan, C.L., Wei, F., Thompson, Carl V., Lee, J.H., Marieb, T., Maiz, J., Pey, Kin Leong, Choi, Wee Kiong Fatal Void Size Comparisons in Via-Below and Via-Above Cu Dual-Damascene Interconnects, http://dspace.mit.edu/
4. Thrasher S., Capasso C., Zhao L., Hermandez R., Mulski P., Rose S., Nguyen T., Kawasaki H., "Blech effect in single-inlaid Cu interconnects", IEEE IITC, 2001.
5. Arnaud L., "Electromigration threshold length effect in dual damascene copper oxide interconnects", IEEE IRPS, 2002.