Stretching the limits of clock-gating efficiency in server-class processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 238-242

  Jacobson, Hans ^a   Bose, Pradip ^a   Hu, Zhigang ^a   Buyuktosunoglu, Alper ^a   Zyuban, Victor ^a   Eickemeyer, Rick ^b   Eisen, Lee ^b   Griswell, John ^b   Logan, Doug ^b   Sinharoy, Balaram ^b   Tendier, Joel ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK-GATINGS; ELASTIC PIPELINES; POWER REDUCTION; WORKLOAD EXECUTIONS;

CLOCKS; ELASTICITY; ELECTRIC CURRENTS; ELECTRIC POWER SYSTEMS; PIPELINES; PROGRAM PROCESSORS;

SERVERS;

EID: 28444498110     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.33     Document Type: Conference Paper

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