A VLSI architecture for minimizing the transmission power in OFDM transceivers

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2003, Pages 308-311

  Babionitakis, K ^a   Dagres, Y ^a   Nakos, K ^a   Reisis, D ^a  

^a UNIVERSITY OF ATHENS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

MINIMAL AREA; OFDM TRANSCEIVER; PERFORMANCE GAIN; TRANSMISSION PARAMETERS; TRANSMISSION POWER; TURBO-CODED; VLSI ARCHITECTURES; WIRELESS APPLICATION; FIELD PROGRAMMABLES;

ARCHITECTURE; FREQUENCY ALLOCATION; OPTIMIZATION; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; ORTHOGONAL FUNCTIONS; QUALITY OF SERVICE; WIRELESS TELECOMMUNICATION SYSTEMS; FREQUENCY DIVISION MULTIPLEXING; RADIO TRANSCEIVERS; VLSI CIRCUITS;

VLSI CIRCUITS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

EID: 28444474998     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2003.1302038     Document Type: Conference Paper

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