A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use

Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS

Volumn , Issue , 2004, Pages 319-323

  Marcus, Guillermo ^a   Hinojosa, Patricia ^a   Avila, Alfonso ^a   Nolazco Flores, Juan ^a  

^a SCHOOL OF ENGINEERING AND SCIENCES   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER HARDWARE; EDUCATION; NUMBER THEORY; PRECISION ENGINEERING;

ADDER/SUBTRACTORS; HARDWARE DESCRIPTIONS; MULTIPLIERS; VHDL;

ADDERS;

EID: 28444450481     PISSN: 15416275     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Guillermo Marcus, Disen̄o Implementation de un Coprocesador Basado en FPGA para el Reconocedor de Voz SPHINX, MSc. Thesis. ITESM, 2003.
2. Gerhard Lienbart, Andreas Kugel and Reinhard Manner, Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations, Field-Programmable Custom Computing Machines, 2002. Proceedings. 10th Annual IEEE Symposium on, 22-24 April 2002.
3. Behrooz Parhami, Computer Arithmetic: Algorions and Hardware Designs, 1st ed. Oxford; Oxford University Press, 2000.
4. IEEE Standards Board, IEEE-754, IEEE Standard for Binary Floatingpoint Arithmetic, New York: IEEE, 1985.
5. FPGA Processors Group, mpRACE Coprocessor, at http://www-li5.ti.uni- mannbeim.de/fpga/?race/. Universit'at Mannheim Mannheim, Germany.
6. Xilinx Inc, ISE, at http://www.xilinx.com
7. Carnegie Mellon University, SPHINX and SPHINX Irian, at http://www.speech.cs.cmu.edu/
8. Mentor Graphics Inc, FPGA Advantage, at http://www.mentor.com/fpga- advantage/
9. Rudolf Usselmann, Floating Point Unit, at http://www.opencorcs.org/ projects.cgi/web/fpu/overview or http://www.ASICS.ws