Improvement of light-load efficiency using width-switching scheme for CMOS transistors

IEEE Power Electronics Letters

Volumn 3, Issue 3, 2005, Pages 105-110

  Musunuri, Surya ^a,b   Chapman, Patrick L ^a,c  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Low power converters; Monolithic converters; Width switching

Indexed keywords

CMOS BUCK CONVERTERS; WIDTH-SWITCHING SCHEME;

ELECTRIC INVERTERS; ELECTRIC LOADS; SWITCHING;

CMOS INTEGRATED CIRCUITS;

EID: 28444445633     PISSN: 15407985     EISSN: None     Source Type: Journal    
DOI: 10.1109/LPEL.2005.859769     Document Type: Article

References (16)

1. S. Musunuri and P. L. Chapman, "Multi-layer spiral inductor design for monolithic DC-DC converters," in Proc. IEEE Industry Applications Conf., vol. 2, 2003, pp. 1270-1275.
2. S. Musunuri, P. L. Chapman, J. Zou, and C. Liu, "Inductor design for monolithic DC-DC converters," in Proc. IEEE Power Electronics Specialist Conf., vol. 1, 2003, pp. 227-232.
3. P. Favrat, P. Deval, and M. J. Declercq, "A high-efficiency CMOS voltage doubler," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, Mar. 1998.
4. M. Borah, R. M. Owens, and M. J. Irwin, "Transistor sizing for low power CMOS circuits," IEEE Trans. Computer-Aided Design, vol. 15, no. 6, pp. 665-671, Jun. 1996.
5. M. Borah, M. J. Irwin, and R. M. Owens, "Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering," in Proc. 8th Int. Conf. VLSI Design, 1995, pp. 294-298.
6. R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti, and P. L. Rolandi, "Power efficient charge pump in deep submicron standard CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1068-1071, Jun. 2003.
7. A. J. Stratakos, S. R. Sanders, and R. W. Brodersen, "A low-voltage CMOS DC-DC converter for a portable battery-operated system," in Proc. 25th Annu. IEEE Power Electronics Specialists Conf., 1994, pp. 619-626.
8. V. Kurson, S. G. Narendra, V. K. De, and E. G. Friedman, "Monolithic DC-DC converter analysis and MOSFET gate voltage optimization," Proc. Fourth Int. Symp. Quality Electronic Design, pp. 279-284, 2003.
9. R. K. Williams, W. Grabowski, A. Cowell, M. Darwish, and J. Berwick, "The dual-gate W-switched power MOSFET: A new concept for improving light load efficiency in DC/DC converters," in Proc. IEEE Int. Symp. Power Semiconductor Devices and IC's, 1997, pp. 193-196.
10. D. Guckenberger and K. Kornegay, "Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology," in Proc. Int. Symp. Low Power Electronics and Design, 2003, pp. 449-454.
11. S.-H. Jung, N.-S. Jung, J.-T. Hwang, and G.-H. Cho, "An integrated CMOS DC-DC converter for battery-operated systems," in Proc. IEEE Power Electronics Specialists Conf., vol. 1, 1999, pp. 43-47.
12. M. Mino, K. Tsukamoto, K. Yanagisawa, A. Tago, and T. Yachi, "A compact buck-converter using a thin-film inductor," in Proc. Eleventh Annu. Applied Power Electronics Conf. Expo., vol. 1, 1996, pp. 422-426.
13. Y. Katayama, S. Sugahara, H. Nakazawa, and M. Edo, "High-power- density MHz-switching monolithic DC-DC converter with thin-film inductor," in Proc. IEEE Power Electronics Specialists Conf., vol. 3, 2000, pp. 1485-1490.
14. S. Musunuri and P. L. Chapman, "Fabrication and characterization of PDMA inductors," in Proc. 35th Annu. IEEE Power Electronics Specialists Conf., 2004 (PESC 04), vol. 6, 2004, pp. 4460-4466.
15. A. C. Jan, M. Rabaey, and B. Nikolic, Digital Integrated Circuits. Upper Saddle River, NJ: Prentice-Hall, 2003.
16. The MOSIS Service. [Online]. Available: http://www.mosis.org