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Volumn , Issue , 2003, Pages 719-722

A 75mW 10bit 120MSample/s parallel pipeline ADC

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITOR MISMATCH; CMOS TECHNOLOGY; DIGITAL CALIBRATIONS; GAIN AND OFFSET; LOW-POWER DESIGN; LOW-POWER DISSIPATION; PARALLEL PIPELINE ADC; PSEUDO DIFFERENTIAL;

EID: 28344445051     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257236     Document Type: Conference Paper
Times cited : (14)

References (7)
  • 1
    • 0013396689 scopus 로고    scopus 로고
    • Low-power area-efficient design of embedded high-speed a/d converters
    • D. Miyazaki, S. Kawahito, "Low-Power Area-Efficient Design of Embedded High-Speed A/D Converters, " IEICE Trans. Electronics, vol. E83-C, no. ll, pp. l724-1732, 2000.
    • (2000) IEICE Trans. Electronics , vol.E83-C , Issue.11
    • Miyazaki, D.1    Kawahito, S.2
  • 2
    • 0036106114 scopus 로고    scopus 로고
    • A 16mw 30msamples/s 10b pipelined a/d converter using a pseudo-differential architecture
    • Feb
    • D. Miyazaki, M. Furuta, S. Kawahito, "A 16mW 30MSamples/s 10b Pipelined A/D Converter Using a Pseudo-Differential Architecture, " Dig. of Tech. papers, Int. Solid-State Circuits Conf., no. l0. 5, pp. l74-175, Feb. 2002.
    • (2002) Dig. of Tech. Papers, Int. Solid-State Circuits Conf. , Issue.105 , pp. 174-175
    • Miyazaki, D.1    Furuta, M.2    Kawahito, S.3
  • 3
    • 0036670375 scopus 로고    scopus 로고
    • A digital calibration technique for capacitor mismatch for pipelined analog-to-digital converters
    • Aug
    • M. Furuta, S. Kawahito, D. Miyazaki, "A Digital Calibration Technique for Capacitor Mismatch for Pipelined Analog-to-Digital Converters, ", IEICE Trans, on Electronics, VoI. E85-C, No. 8, pp. l562-1568, Aug. 2002.
    • (2002) IEICE Trans, on Electronics , vol.E85C , Issue.8
    • Furuta, M.1    Kawahito, S.2    Miyazaki, D.3
  • 4
    • 0035392381 scopus 로고    scopus 로고
    • A 10-bit 200-ms/s cmos parallel pipelined a/d converter
    • July
    • Lauri Sumanen, Mikko Waltari and Kari A. I. Halonen, "A 10-bit 200-MS/s CMOS Parallel Pipelined A/D Converter", IEEE JSSC, ppl048-1055, Vol. 36, No. 7, July. 2001.
    • (2001) IEEE JSSC, ppl048-1055 , vol.36 , Issue.7
    • Sumanen, L.1    Waltari, M.2    Halonen, K.A.I.3
  • 5
    • 0026141224 scopus 로고
    • A 13-b 2 5-mhz self-calibrated pipelined a/d converter in 3u-m cmos
    • Mar
    • Yuh-Min Lin, Beomsup Kim, Paul R. Gray, "A 13-b 2. 5-MHz Self-Calibrated Pipelined A/D Converter in 3u-m CMOS", IEEE JSSC, pp628-636, Vol. 26, No. 4, Mar. 1991.
    • (1991) IEEE JSSC , vol.26 , Issue.4 , pp. 628-636
    • Lin, Y.-M.1    Kim, B.2    Gray, P.R.3
  • 6
    • 0028417146 scopus 로고
    • A 12-b 600ks/s digitally self calibrated pipelined algorithmic adc
    • Apr
    • Hae-Seung Lee, "A 12-b 600ks/s Digitally Self Calibrated Pipelined Algorithmic ADC", IEEE JSSC, pp509-5I5, Vol. 29, No. 4, Apr. 1994.
    • (1994) IEEE JSSC , vol.29 , Issue.4
    • Lee, H.-S.1
  • 7
    • 0036113498 scopus 로고    scopus 로고
    • A lobit 120msample/s time-interleaved analog-to-digital converter with digital background calibration
    • Feb
    • S. M. Jamal, D. Fu, P. J. Hurst, S. H. Lewis, "A lObit 120MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration, " Dig. of Tech. papers, Int. Solid-State Circuits Conf., no. l0. 4, pp. l73-174, Feb. 2002.
    • (2002) Dig. of Tech. Papers, Int. Solid-State Circuits Conf. , Issue.104 , pp. 173-174
    • Jamal, S.M.1    Fu, D.2    Hurst, P.J.3    Lewis, S.H.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.