A low-noise low-voltage CT ΔΣ modulator with digital compensation of excess loop delay

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Fontaine, Paul ^a   Mohieldin, Ahmed N ^a   Bellaouar, Abdellatif ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144441805     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. B. Nauta, "A CMOS Transconductance-C Filter Technique for Very High Frequencies," IEEE J. Solid-State Circuits, vol. 27, pp. 142-153, Feb., 1992.
2. + Analog Front End for CO Applications with 75mW per Channel built in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp 402-403, Feb., 2004.
3. S. Yan and E. Sanchez-Sinencio, "A CT ΔΣ Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth," IEEE J. Solid-State Circuits, vol. 39, pp. 75-86, Jan., 2004.