An 80MHz 4x oversampled cascaded ΔΣ-pipelined ADC with 75dB DR and 87dB SFDR

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Bosi, Alessandro ^a   Panigada, Andrea ^a   Cesura, Giovanni ^a   Castello, Rinaldo ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CMOS INTEGRATED CIRCUITS; FORMAL LOGIC; LINEARIZATION; SIGNAL TO NOISE RATIO;

BACKGROUND DIGITAL LINEARIZATION; NOISE-CANCELLATION ALGORITHMS; PIPELINED ADC;

MODULATORS;

EID: 28144441360     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)