Fast parallel multiplication using redundant quarternary number system

Parallel Processing Letters

Volumn 7, Issue 1, 1997, Pages 13-23

  Mallkade, ^a  

^a UNIVERSITY OF KALYANI   (India)

Author keywords

Carry propagation free adder; Quartemary integer multiplication; Redundant number system; Signed dieit number representation; VLSI

Indexed keywords

EID: 28144439279     PISSN: 01296264     EISSN: None     Source Type: Journal    
DOI: 10.1142/s0129626497000048     Document Type: Article

References (2)

1. S. Nakamura, Algorithms for iterative array multiplication, IEEE Trans. Comput. 35 (1986) 713-719.
2. N. Takagi, H. Yassura and S. Yajima, High speed VLSI multiplication algorithm with a redundant binary addition tree, IEEE Trans. Comput. 34 (1985) 789-796.