A split-ADC architecture for deterministic digital background calibration of a 16b 1MS/s ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  McNeill, John ^a   Coln, Michael ^a   Larivee, Brian ^b  

^a WORCESTER POLYTECHNIC INSTITUTE   (United States)

^b ANALOG DEVICES INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIE SIZE; DIGITAL BACKGROUND; SELF-CALIBRATION; SUB-SYSTEM;

ALGORITHMS; CALIBRATION; CMOS INTEGRATED CIRCUITS; DIES;

ANALOG TO DIGITAL CONVERSION;

EID: 28144434010     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)