Clocking and circuit design for a parallel I/O on a first-generation CELL processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Chang, Ken ^a   Pamarti, Sudhakar ^a   Kaviani, Kambiz ^a   Alon, Elad ^a,b   Shi, Xudong ^a   Chin, T J ^a   Shen, Jie ^a   Yip, Gary ^a   Madden, Chris ^a   Schmitt, Ralf ^a   Yuan, Chuck ^a   Assaderaghi, Fari ^a   Horowitz, Mark ^a,b  

^a Rambus   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CIRCUIT DESIGN; HIGH-SPEED RECEIVERS; RECEIVER SENSITIVITY;

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; INTEGRATED CIRCUIT LAYOUT; JITTER; PROGRAM PROCESSORS; SIGNAL RECEIVERS; SILICON ON INSULATOR TECHNOLOGY;

INPUT OUTPUT PROGRAMS;

EID: 28144431703     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)