A reliable failure analysis methodology in analyzing the elusive gate-open failures

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2005, Pages 185-189

  Remo, Nilda C ^a   Fernandez, Jean Carla M ^a  

^a Fairchild Semiconductor Philippines Incorporated   (Philippines)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; ELECTRONIC EQUIPMENT TESTING; FAILURE (MECHANICAL); GATES (TRANSISTOR); STRESSES; WIRE;

GATE CONTACT INTERFACES; GATE WIRE; GATE-OPEN FAILURES; WIRE BONDS;

FAILURE ANALYSIS;

EID: 28044473369     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. th ASEMEP National Technical Symposium, Manila, 2004
2. N.C. Remo, J.C. Fernandez, "A Reliable Failure Analysis Methodology in Analyzing the Elusive Gate-Open Failures", Fairchild Company Internal, 2004
3. C. Suico, "Floating Gate Experiment (In Relation to Gate Lifting Issue), Fairchild Company Internal, 2000
4. R. Baga, "Gate Open / Continuous ID Experiment", Fairchild Company Internal, 2001
5. N. Remo, Failure Analysis Report CB0409105 Rev. B, Fairchild Company Internal, 2001
6. N. Remo, Failure Analysis Report CB0414307, Fairchild Company Internal, 2004
7. N. Remo, Failure Analysis Report CB0422209, Fairchild Company Internal, 2004