A page fault equation for modeling the effect of memory size

Performance Evaluation

Volumn 63, Issue 2, 2006, Pages 99-130

  Tay, Y C ^a   Zou, Min ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Capacity planning; Database buffer management; Invariant; Memory allocation; Memory requirement; Power control; Processor cache design

Indexed keywords

COMPUTER PROGRAMMING; COMPUTER SIMULATION; DATABASE SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; POWER CONTROL; REAL TIME SYSTEMS; STORAGE ALLOCATION (COMPUTER);

CAPACITY PLANNING; DATABASE BUFFER MANAGEMENT; INVARIANT; MEMORY REQUIREMENT; PROCESSOR CACHE DESIGN;

DATA STORAGE EQUIPMENT;

EID: 28044455034     PISSN: 01665316     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.peva.2005.01.007     Document Type: Article

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