An hardware efficient deblocking filter for H.264/AVC

Digest of Technical Papers - IEEE International Conference on Consumer Electronics

Volumn , Issue , 2005, Pages 235-236

  Cheng, Chao Chung ^a   Chang, Tian Sheuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; CONSUMER ELECTRONICS; REAL TIME SYSTEMS; STANDARDS; VLSI CIRCUITS;

DEBLOCKING FILTERS; H.264/AVC; HARDWARE IMPLEMENTATION; REAL-TIME DEBLOCKING;

SIGNAL FILTERING AND PREDICTION;

EID: 28044450124     PISSN: 0747668X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y.-L. Lee and H. W. Park, "Loop filtering and post-filtering for low-bitrates moving picture coding," Signal Processing: Image Commun., vol. 16, pp. 871-890, 2001.
2. S. D. Kim, J. Yi, H. M. Kim, and J. B. Ra, "A deblocking filter with two separate modes in block-based video coding," IEEE Trans. Circuits Syst. Video Technol., vol. 9, pp. 156-160, Feb. 1999.
3. Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264/ ISO/ IEC 14496-10 AVC), Mar. 2003.
4. P. List, A. Joch, J. Lainema, G. Bjøntegaard, and M. Karczewicz, "Adaptive deblocking filter," IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, Jul. 2003.
5. H.264/AVC reference software JM7.2, Jul. 2003
6. Y.-W. Huang, T.-W. Chen. B.-Y. Hsieh, T.-C. Wang, T.-H. Chang, L.-G. Chen, "Architecture design for deblocking filter in H.264/JVT/AVC," Proc. of Multimedia and Expo, vol. 1, Jul. 2003 pp. 693-696.