Implementation of PBS_LMS algorithm for adaptive filters on FPGA

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn A, Issue , 2004, Pages

  Majdar, Reza Seifi ^a   Eshghi, Mohammad ^a  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SCIENCE; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; ELECTRICAL ENGINEERING; FIELD PROGRAMMABLE GATE ARRAYS; PROGRAM PROCESSORS;

ARITHMETIC OPERATIONS; MOTOROLA (CO); TRANSVERSAL ADAPTIVE FILTERS; XILINX (CO);

ADAPTIVE FILTERING;

EID: 27944470591     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. M.eshghi, "A parallel binary structured LMS algorithm for transversal adaptive filter", Ph.D thesis, Ohio state University, 1994
2. S. Haykin, "Adaptive filter theory", Englewood Clifton, NJ: Prentice-Hall, 19986
3. S. Park," A VLSI architecture for adaptive signal processing", IEEE proceedings of southeastcon, 1991
4. J.Benesty, P.Duhaamel,"A fast Exact Least Mean Square Adaptive Algorithm", IEEE Trans.on signal processing, vol. 40, NO. 12, December 1992
5. Altera, Stratix Programmable Logic Device Family Data Sheet, Data Sheet DS-STXFAMLY-2 1, Altera, Inc., August, 2002
6. Xilinx, Virtex™-II Platform FPGAs Complete Data Sheet, Data Sheet DS031-4 (v2.0), Xilinx, Inc., August 1, 2003
7. Motorola, Incorporated, DSP56300 FAMILY MANUAL 24-Bit Digital Signal Processor, November 2000