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Volumn 2, Issue 2, 1997, Pages 135-150

Hmap: A fast mapper for EPGAs using extended GBDD hash tables

Author keywords

Area minimization; Decomposition; Field programmable gate arrays (FPGAs); Technology mapping

Indexed keywords


EID: 27944460068     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/253052.253098     Document Type: Article
Times cited : (2)

References (19)
  • 1
    • 0017983865 scopus 로고
    • Binary decision diagrams
    • AKERS, S. B. 1978. Binary decision diagrams. IEEE Trans. Comput. C-27, 6 (June), 509-516.
    • (1978) IEEE Trans. Comput. , vol.27 C , Issue.6 JUNE , pp. 509-516
    • Akers, S.B.1
  • 4
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • BRYANT, R. 1986. Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C-35, 8 (Aug.), 677-691.
    • (1986) IEEE Trans. Comput. , vol.35 C , Issue.8 AUG , pp. 677-691
    • Bryant, R.1
  • 10
    • 0026174956 scopus 로고
    • Amap: A technology mapper for selector-based field-programmable gate arrays
    • San Francisco, June
    • KARPLUS, K. 1991. Amap: A technology mapper for selector-based field-programmable gate arrays. In Proceedings of the 28th ACM/IEEE Design Automation Conference (San Francisco, June), 244-247.
    • (1991) Proceedings of the 28th ACM/IEEE Design Automation Conference , pp. 244-247
    • Karplus, K.1
  • 11
    • 0023210698 scopus 로고
    • DAGON: Technology binding and local optimization by DAG matching
    • Miami Beach, June-July
    • KEUTZER, K. 1987. DAGON: Technology binding and local optimization by DAG matching. In Proceedings of the 24th ACM/IEEE Design Automation Conference (Miami Beach, June-July), 341-347.
    • (1987) Proceedings of the 24th ACM/IEEE Design Automation Conference , pp. 341-347
    • Keutzer, K.1
  • 13
    • 0027591119 scopus 로고
    • Algorithms for technology mapping based on binary decision diagrams and on Boolean operations
    • MAILHOT, F. AND DE MICHELI, G. 1993. Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. IEEE Trans. Comput. Aided Des. 12, 5 (May), 599-620.
    • (1993) IEEE Trans. Comput. Aided Des. , vol.12 , Issue.5 MAY , pp. 599-620
    • Mailhot, F.1    De Micheli, G.2
  • 14
    • 0027294298 scopus 로고
    • MIM: Logic module independent technology mapping for design and evaluation of antifuse-based FPGAs
    • Dallas, June
    • MEHENDALE, M. 1993. MIM: Logic module independent technology mapping for design and evaluation of antifuse-based FPGAs. In Proceedings of the 30th ACM/IEEE Design Automation Conference (Dallas, June), 219-223.
    • (1993) Proceedings of the 30th ACM/IEEE Design Automation Conference , pp. 219-223
    • Mehendale, M.1
  • 18
    • 0003623384 scopus 로고
    • Ph.D. Thesis, U.C. Berkeley, April, and Memorandum UCB/ERL M89/49
    • RUDELL, R. 1989. Logic synthesis for VLSI design. Ph.D. Thesis, U.C. Berkeley, April, and Memorandum UCB/ERL M89/49.
    • (1989) Logic Synthesis for VLSI Design
    • Rudell, R.1
  • 19
    • 0027627411 scopus 로고
    • Synthesis methods for field programmable gate arrays
    • SANGIOVANNI-VINCENTELLI, A., EL GAMAL, A., AND ROSE, J. 1993. Synthesis methods for field programmable gate arrays. Proc. IEEE 81, 7 (July), 1057-1083.
    • (1993) Proc. IEEE , vol.81 , Issue.7 JULY , pp. 1057-1083
    • Sangiovanni-Vincentelli, A.1    El Gamal, A.2    Rose, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.