Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction

IEEE Transactions on Reliability

Volumn 54, Issue 3, 2005, Pages 459-467

  Tiwari, Anurag ^a   Tomko, Karen A ^b  

^a SUN MICROSYSTEMS   (United States)

^b University of Cincinnati   (United States)

Author keywords

Fault tolerant FPGA design; FSM reliability; Single event upset (SEU); Soft errors

Indexed keywords

FAULT TOLERANT COMPUTER SYSTEMS; FINITE AUTOMATA; FLIP FLOP CIRCUITS; PROBABILITY; REDUNDANCY; RELIABILITY THEORY;

FAULT TOLERANT FPGA DESIGN; FINITE STATE MACHINE RELIABILITY; SINGLE EVENT UPSET (SEU); SOFT ERRORS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 27844540384     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2005.853438     Document Type: Article

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