Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization

IEEE Transactions on Instrumentation and Measurement

Volumn 54, Issue 5, 2005, Pages 1662-1677

  Das, Sunil R ^a,b   Ramamoorthy, Chittoor V ^c   Assaf, Mansour H ^a   Petriu, Emil M ^a   Jone, Wen Ben ^d   Sahinoglu, Mehmet ^b  

^a UNIVERSITY OF OTTAWA   (Canada)

^b TROY UNIVERSITY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d 705 Engineering Research Center   (United States)

Author keywords

ATALANTA; Built in self test (BIST); COMPACTEST; FSIM; Full scan circuits; MinTest; Nonexhaustive (deterministic compact and pseudorandom) test sets; Sequence characterization; Space compaction; VLSI circuits

Indexed keywords

BUILT-IN SELF TEST; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; PROBABILITY; RANDOM PROCESSES; VLSI CIRCUITS;

FULL SCAN CIRCUITS; NONEXHAUSTIVE TEST SETS; SEQUENCE CHARACTERIZATION; SPACE COMPACTION;

INTEGRATED CIRCUIT TESTING;

EID: 27644582387     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2005.855085     Document Type: Article

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