A 1.9GHz SiGe BiCMOS PHS transceiver with an integrated PA and a fast settling PLL

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2005, Pages 277-280

  Mostafa, Mohamed A I ^a   Quek, Chee K ^a   El Moznine, Abdellatif ^a   Roberts, William ^a   Romney, Matt ^a   Walker, David ^a   Stegmeir, Dave ^a   Tran, Kien ^a   King, Nathaniel ^a   Farahvash, Shayan ^a   Koupal, Robert ^a  

^a Micro Linear Corporation   (United States)

Author keywords

Low IF Architecture; PHS; PLL; Power Amplifier; SiGe BiCMOS; Transceiver

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FILTERS; PHASE LOCKED LOOPS; POWER AMPLIFIERS;

LOW-IF ARCHITECTURE; PHS; SIGE BICMOS;

TRANSCEIVERS;

EID: 27644523528     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Hisayasu Sato, et. al, "A 1.9GHz Single Chip IF Transceiver for Digital Cordless Phones", IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, Dec 1996, pp. 1974-1980.
2. Huainan Ma, et. al., "A GaAs Upconverter MMIC with an Automatic Gain Control Amplifier for 1.9GHz PHS", IEEE Journal of Solid-State Circuits, Vol. 33, No. 9, Sep 1998, pp. 1297-1305.
3. Shoji Otaka, et. al., "A 1.9GHz Si-Bipolar Variable Attenuator for PHS transmitter", IEEE Journal of Solid-State Circuits, Vol. 32, No. 9, Sep 1997, pp. 1424-1429.
4. Tetsuro Itakura, "A 2.7V, 200kHz, 49dBm, Stopband IIP3, Low Noise, Fully Balanced Gm-C filter 1C", IEEE Journal of Solid-State Circuits, Vol. 34, No. 8, Aug 1999, pp.1155-1159.
5. R.S Hughes, "Logarithmic Amplification with Application to Radar and EW," Dedham, MA, Artech House, 1986.
6. Bar-Giora Goldberg, "Digital Frequency Synthesis Demystified," Newnes, 1999.