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Volumn , Issue , 2005, Pages 259-263
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Speedup of Clos packet switches that provide delay guarantees
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
CROSSBAR EQUIPMENT;
DELAY CIRCUITS;
ELECTRIC LOADS;
TELECOMMUNICATION TRAFFIC;
SHARED BUFFERS;
SWITCH UTILIZATION;
SWITCHING ELEMENTS (SE);
TRAFFIC LOADS;
PACKET SWITCHING;
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EID: 27644504420
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/hpsr.2005.1503234 Document Type: Conference Paper |
Times cited : (1)
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References (10)
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