A VLSI architecture for watermarking in a secure still digital camera (S 2DC) design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 7, 2005, Pages 808-817

  Mohanty, Saraju P ^a,b,e   Ranganathan, Nagarajan ^a,c,f,g   Namballa, Ravi K ^d  

^a IEEE   (United States)

^b UNIVERSITY OF NORTH TEXAS   (United States)

^c University of South Florida   (United States)

^d Aeolus Systems LLC   (United States)

^e ASSOCIATION FOR COMPUTING MACHINERY   (United States)

^f UNIVERSITY OF SOUTH FLORIDA   (United States)

^g VLSI Society of   (India)

Author keywords

And in watermarking; Digital watermarking; JPEG encoder; Spatial do main watermarking; Still digital camera

Indexed keywords

AND IN WATERMARKING; JPEG ENCODER; SPATIAL-DO-MAIN WATERMARKING; STILL DIGITAL CAMERA;

CAMERAS; COMPUTER ARCHITECTURE; COPYRIGHTS; DECODING; DIGITAL WATERMARKING; INTEGRATION; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS;

VLSI CIRCUITS;

EID: 27644488127     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.850095     Document Type: Article

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