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Volumn , Issue , 2005, Pages 461-464

A 40GHz 2.1V static frequency divider in SiGe using a low-voltage latch topology

Author keywords

Flip flops; Frequency conversion; High speed integrated circuits; Logic design

Indexed keywords

FREQUENCY CONVERSIONS; SWITCHED EMITTERS;

EID: 27644475226     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (10)
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    • Miller, R.L.1
  • 2
    • 0034430927 scopus 로고    scopus 로고
    • A 79GHz dynamic frequency divider in SiGe bipolar technology
    • Feb.
    • H. Knapp, et al., "A 79GHz dynamic frequency divider in SiGe bipolar technology," ISSCC Dig. Tech. Papers, pp. 208-209, Feb. 2000.
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    • Knapp, H.1
  • 3
    • 28144443227 scopus 로고    scopus 로고
    • 7-1 PRBS generator in SiGe using a low-voltage logic family
    • Feb.
    • 7-1 PRBS generator in SiGe using a low-voltage logic family," ISSCC Dig. Tech. Papers, pp. 340-341, Feb. 2005.
    • (2005) ISSCC Dig. Tech. Papers , pp. 340-341
    • Kucharski, D.1    Kornegay, K.2
  • 4
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    • Design techniques for low-voltage high-speed digital bipolar circuits
    • Mar.
    • B. Razavi, Y. Ota, and R.G. Swartz, "Design techniques for low-voltage high-speed digital bipolar circuits," IEEE J. Solid-State Circuits, vol. 29, pp. 332-339, Mar. 1994.
    • (1994) IEEE J. Solid-state Circuits , vol.29 , pp. 332-339
    • Razavi, B.1    Ota, Y.2    Swartz, R.G.3
  • 5
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    • Analysis and comparison of low-voltage CML D-latch
    • Sep.
    • M. Alioto, R. Mita, and G. Palumbo, "Analysis and comparison of low-voltage CML D-latch," Proc. ICCS, vol. 2, pp. 737-740, Sep. 2002.
    • (2002) Proc. ICCS , vol.2 , pp. 737-740
    • Alioto, M.1    Mita, R.2    Palumbo, G.3
  • 6
    • 0034225503 scopus 로고    scopus 로고
    • Investigation on low-voltage low-power silicon bipolar design topology for high-speed digital circuits
    • July
    • G. Shuppener, C. Pala, and M. Mokhtari, "Investigation on low-voltage low-power silicon bipolar design topology for high-speed digital circuits," IEEE J. Solid-State Circuits, vol. 35, pp. 1051-1054, July 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 1051-1054
    • Shuppener, G.1    Pala, C.2    Mokhtari, M.3
  • 7
    • 0031075777 scopus 로고    scopus 로고
    • A high-speed, low-power bipolar digital circuit for Gb/s LSI's: Current mirror control logic
    • Feb.
    • K. Kishine, Y. Kobayashi, and H. Ichino, "A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic," IEEE J. Solid-State Circuits, vol. 32, pp. 215-221, Feb. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , pp. 215-221
    • Kishine, K.1    Kobayashi, Y.2    Ichino, H.3
  • 8
    • 0030084277 scopus 로고    scopus 로고
    • Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits
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    • K.M. Sharaf and M.I. Elmasry, "Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits," IEEE J. Solid-State Circuits, vol. 31, pp. 202-211, Feb. 1996.
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    • Sharaf, K.M.1    Elmasry, M.I.2
  • 9
    • 1042289136 scopus 로고    scopus 로고
    • A 51GHz master-slave latch and static frequency divider in 0.18μm SiGe BiCMOS
    • Sep.
    • A. Rylyakov, "A 51GHz master-slave latch and static frequency divider in 0.18μm SiGe BiCMOS," Proc. BCTM, pp. 75-77, Sep. 2003.
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  • 10
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    • Static bipolar 11GHz SiGe divider with 1V power supply
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    • S. Rylov and A. Rylyakov, "Static bipolar 11GHz SiGe divider with 1V power supply," Proc. BCTM, pp. 79-81, Sep. 2003.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.