FOCUS: An Experimental Environment for Fault Sensitivity Analysis

IEEE Transactions on Computers

Volumn 41, Issue 12, 1992, Pages 1515-1526

  Choi, Gwan S ^a   Iyer, Ravishankar K ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Design for dependability; empirical models; error propagation; fault injection; faults; statistical analysis; transient; VLSI simulation

Indexed keywords

EID: 27544463457     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.214660     Document Type: Article

References (28)

1. J. Arlat, Y. Crouzet, and J. Laprie, “Fault-injection for dependability validation,” LAAS Res. Rep. no. 88–363, Dec. 1988.
2. H. Ball and F. Hardy, “Effects and detection of intermittent failures in digital systems,” in FJCC, AFIPS Conf Proc., vol. 35, 1969 pp. 329–335.
3. R. Chillarege and R. Iyer, “Measurement-based analysis of error latency,” IEEE Trans. Comput., vol. C-36, no. 5, May 1987.
4. V. Carreno, G. Choi, and R. Iyer, “Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system,” NASA Tech. Memo. 4231, Nov. 1990.
5. G. Choi, R. Iyer, R. Saleh, and V. Carreno, “Fault behavior model for an avionic microprocessor,” in Proc., Int. Working Conf. Dependable Comput. For Critical Appl., Santa Barbara, CA, Aug. 1989.
6. B. Courtois, “Some results about the efficiency of simple mechanisms for the detection of microcomputer malfunctions,” in Dig., FTCS-9, Ninth Int. Symp. Fault Tolerant Comput., June 1979, 71–74.
7. J. Cusick, R. Koga, W. Kolasinski, and C. King, “SEU vulnerability of the Zilog Z-80 and NSC-800 microprocessors,” IEEE Trans. Nucl. Sci., vol. NS-32, pp. 4206–4211, Dec. 1985.
8. E. W. Czeck, “On the prediction of fault behavior based on workload,” Ph.D. dissertation, Dep. Elec. and Comput. Eng., Carnegie Mellon Univ., Apr. 19, 1991.
9. P. Duba and R. Iyer, “Transient fault behavior in a microprocessor: A case study,” in 1988 ICCD Proc., Oct. 1988.
10. R. Glaser and G. Masson, “Transient upsets in microprocessor controllers,” in Dig., FTCS-11, Eleventh Int. Symp. Fault Tolerant Comput., 1981, 165–167.
11. U. Gunneflo, J. Karlsson, and J. Torin, “Evaluation of error detection schemes using fault injection by heavyion radiation,” in Dig., FTCS-19, Nineteenth Int. Fault
12. R. Iyer and D. Rossetti, “A measurement-based model for workload dependence of CPU errors,” IEEE Trans. Comput., vol. C-35, pp. 511–519, June 1986.
13. R. Johnson, S. Diehl-Nagle, and J. Hauser, “Simulation approach for modeling single event upsets on advanced CMOS SRAMS,” IEEE Trans. Nucl. Sci., vol. NS-32, 4122–4127, Dec. 1985.
14. J. Karlsson, U. Gunneflo, and J. Torin, “The effects of heavyion induced single event upsets in the MC6809E microprocessor,” in Proc. 4th Int. Conf. Fault-Tolerant Comput. Syst., GI/ITG/GMA, Baden, W. Germany, 1989.
15. R. Koga, W. Kolasinski, and M. Marra, “Techniques of microprocessor testing and SEU-rate prediction,” IEEE Trans. Nucl. Sci., vol. NS-32, pp. 4219–4224, Dec. 1985.
16. J. Lala, “Fault detection isolation and reconfiguration in FTMP: Methods and experimental results,” in Proc. 5th AIAA/IEEE Digital Avion. Syst. Conf. (DASC), 1983, 21.3.1-21.3.9.
17. D. Lomelino and R. Iyer, “Error propagation in a digital avionic processor: A simulation-based study,” in Proc. Real Time Syst. Symp., Dec. 1986, pp. 218–225.
18. T. May and M. Woods, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Trans. Electron Devices, vol. ED-26, pp. 2–9, Jan. 1979.
19. R. McPartland, “Circuit simulations of alpha-particle-induced soft errors in dynamic RAM's,” IEEE J. Solid-State Circuits, vol. SSC-16, pp. 31–34, Feb. 1981.
20. G. Messenger, “Collection of charge on junction nodes from ion tracks,” IEEE Trans. Nucl. Sci., vol. NS-29, Dec. 1982.
21. D. Nichols, W. Price, W. Kolasinski, R. Koga, J. Pickel, J. Blandford, Jr., and A. Waskiewicz, “Trends in part susceptibility to single event upset” IEEE Trans. Nucl. vol. Dec. 1985.
22. R. Saleh, “Nonlinear relaxation algorithms for circuit simulation,” Memo. UCB/ERL M87/21, Electronics Res. Lab., Univ. of California, Berkeley, 1987.
23. M. Schmid, R. L. Trapp, A. Davidoff, and G. Masson, “Upset exposure by means of abstraction verification,” in Dig., FTCS-12, Eleventh Int. Fault Tolerant 1982, 237 – 244.
24. K. Shin and Y. Lee, “Error detection process—Model, design, and its impact on computer performance,” IEEE Trans. Comput., vol. C-33, pp. June 1984.
25. —, “Measurements of fault latency: Methodology and experimental results,” Tech. Rep. CRL-TR-45-84, Comput. Res. Lab., Univ. of Michigan, Ann Arbor, 1984.
26. M. Schmid, R. Trapp, A. Davidoff, and G. Masson, “Upset exposure by means of abstraction verification,” in Dig. FTCS-12, Eleventh Int. Symp. Fault Tolerant Comput., 1982, 237–244.
27. J. Sosnowski, “Evaluation of transient hazards in microprocessor controllers,” in Dig., FTCS-16, Sixteenth Int. Symp. Fault Tolerant Comput., 1986, pp. 364-369.
28. J. Stephen, T. Sanderson, D. Mapper, J. Farren, R. Harboe-Sorensen, and L. Adams, “A comparison of heavy ion sources used in cosmic ray simulation studies of VLSI circuits,” IEEE Trans. Nucl. Sci., vol. NS-31, no. 6, Dec. 1984.